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I was reading this book "ARM System Developers Guide" by Elsevier and I came across this:

The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications:

Variable cycle execution for certain instructions — Not every ARM instruction executes in a single cycle. For example, load-store-multiple instructions vary in the number of execution cycles depending upon the number of registers being transferred. The transfer can occur on sequential memory addresses, which increases performance since sequential memory accesses are often faster than random accesses. Code density is also improved since multiple register transfers are common operations at the start and end of functions.

Any other ARM instructions you guys can point out which take variable cycles to execute?

HaggarTheHorrible
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1 Answers1

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Cycle timings are micro architecture dependent, so you need to check particular implementation's technical reference manual (TRM). For example for Cortex-A9, it is described as being quite complicated.

The complexity of the Cortex-A9 processor makes it impossible to calculate precise timing information manually. The timing of an instruction is often affected by other concurrent instructions, memory system activity, and additional events outside the instruction flow.

However on the same document there are precise timings for data-processing, load and store, multiplication and some information about branch and serialization instructions.

For example from the same document you can see if shifting is involved AND instruction may take 1-2 cycles more depending on the shift source, which might be a constant embedded in instruction or read from a register.

Also next to book's note about load-store-multiple may vary on number of registers involved, they also vary if address is aligned or not.

auselen
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  • +1 and if you look at the axi bus and first think about alignment and the bus width, but then think that this is where the chip vendor comes in and arm has no control, the timing varies widely from the same core used by different vendors in different implementations. All instructions including the most simple (nop) take multiple clock cycles, it is the nature of modern pipelined architectures... – old_timer Oct 27 '12 at 20:54