VHDL state machine is not looping

Question

Fellow SO users,

I'm programming my ADC (ADC0804 which is mounted on a breadboard connected to a Spartan-3 FPGA board). Now, I'm using this ADC to provide digital output for my humidity sensor. The ADC outputs an 8-bit value which I'm displaying on the LEDs on the FPGA board.

Now, I'm writing the state machine in such a way that the ADC would always continue to keep outputting values even when I vary the humidity level. But as for the current implementation I have, eventhough I'm looping back to the first state, I'm not getting a continuous stream of values. I'm only getting one 8-bit value at a time (I.E.; I have to keep pressing the reset button to update the value displayed on the LEDs). The following is my code.

FSM_NEXT_STATE_INIT :   PROCESS (CLK, RST)
                        BEGIN
                        IF (RST = '1') THEN
                           CURR_STATE <= STARTUP;
                        ELSIF (CLK'EVENT AND CLK = '1') THEN
                            CURR_STATE <= NEXT_STATE;
                        END IF;
                       END PROCESS;

START_FSM   :   PROCESS (CURR_STATE, INTR)
                BEGIN

                CASE CURR_STATE IS

                        WHEN STARTUP =>
                            NEXT_STATE <= CONVERT;
                            WR <= '0';
                            READ_DATA <= '0';


                        WHEN CONVERT =>
                            IF (INTR = '0') THEN
                                NEXT_STATE <= READ1;
                            ELSE
                                NEXT_STATE <= CONVERT;
                            END IF;
                            WR <= '1';
                            READ_DATA <= '0';


                        WHEN READ1 =>
                            NEXT_STATE <= READ2;
                            WR <= '1';
                            READ_DATA <= '1';

                        WHEN READ2 =>
                            NEXT_STATE <= STARTUP;
                            WR <= '1';
                            READ_DATA <= '0';

                        WHEN OTHERS =>
                            NEXT_STATE <= STARTUP;
                END CASE;
                END PROCESS;

                PROCESS (CLK, RST)
                BEGIN
                    IF (RST = '1') THEN
                        Y <= (OTHERS => '0');
                    ELSIF (CLK'EVENT AND CLK = '1') THEN
                        IF (READ_DATA = '1') THEN
                            Y <= D7&D6&D5&D4&D3&D2&D1&D0; --Concatenate the 8-bit ADC output
                        END IF;
                    END IF;
                END PROCESS;

You'll notice that in state 'READ2', I'm looping back to the beginning (so that I can keep reading values continuously as the states transition) but somehow I don't think this is working. Could anyone please provide some assistance on how to go about solving this?

Quick rhetorical questions: 1) are you getting stuck in CONVERT because INTR is never asserted? 2) is your FSM going off in the weeds because your reset is not debounced? (you mentioned a reset *button*) — wjl, Oct 06 '12 at 05:44
Hi, INTR is a signal that is asserted by the ADC itself once the conversion is complete. As for the reset button, I'm just using that to manually update the LEDs which output the 8-bit value from the ADC. So, everytime I press the reset button and vary the humidity on the sensor, the value on the LEDs will change. — Triple777er, Oct 06 '12 at 07:01

andrsmllr · Accepted Answer · 2012-10-07T01:03:59.743

2

After a look on the data sheet for the ADC0804 I found following which could be the/a possible reason:

Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR.

Inserting a WAIT state between CONVERT and READ1 might fix the problem.

edited Oct 07 '12 at 01:03

answered Oct 06 '12 at 23:57

andrsmllr

1,231
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Thanks, I can confirm that this is the answer. I've tried using an arudino board by introducing delays and this works! Thanks once again. – Triple777er Oct 07 '12 at 01:00

VHDL state machine is not looping

1 Answers1