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So; on a 64 bit SPARC CPU which is v9 compliant, there exists I know a cas instruction. This operates on single word length values.

I've also seen on the web reference to a casx instruction - but I can't find out anything much more about it.

I'm wondering - is this a double word compare and swap?

And if not, the general question is; IS there a double word compare and swap?

artless noise
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3 Answers3

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CASXA. See The SPARC Architecture Manual.

AProgrammer
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  • CASA swaps 32 bit values. CASXA swaps 64 bit values. Sparc v9 as I understand it is a 64 bit CPU. I'm looking for a double-word CAS, e.g. 128 bits on a 64 bit CPU. I looks then like this does not exist on Sparc. –  Aug 14 '09 at 12:00
  • Ah... the old ambiguity of "word" in an architecture which expand. – AProgrammer Aug 14 '09 at 12:27
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    Yes - I realised when I read the manual, Sparc thinks of word as 32 bits. –  Aug 14 '09 at 12:54
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Also note that casx does exist, however it's a synthetic instruction (i.e. a simplified mnemonic) for casxa. See Table 43 in the aforementioned SPARC Architecture Manual:

Synthetic:   casx [regrs1], regrs2, regrd 
Instruction: casxa [regrs1]#ASI_P, regrs2, regrd 
Description: compare and swap extended
DaveR
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  • Ahh - I *wondered* what Sun meant when they said synthetic instruction. –  Aug 14 '09 at 12:02
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Sparc64 - alone amongst modern CPUs - implements neither double wide CAS nor LL/SC. As such, implementing lock-free code is problematic. There a solutions, but they are solutions to a problem (ABA) which does not exist on other platforms because of their support for CAS or LL/SC. Furthermore, a range of lock-free algorithms cannot be implemented on Sparce because of this limitation.