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I'm supposed to design a system having

  • CPU with a 16 bit wide ADRESS BUS and a 8 bit wide DATA BUS.

In this system I have to my disposal a:

  • RAM with a DATA width of 4 bits, and a ADRESS width of 12 bits.

and a:

  • ROM with a DATA width of 8 bits, and a ADRESS width of 14 bits.

Isn't it a problem that the sizes of the data buses are different when constructing the system? I mean, I know that when using the adress bus you can choose which lines of the bus you want to work with so you can target a specific memory space. But when using the data bus, is it really the same idea? If I have mapped the memory space continuously will programs that run in this system loose data this way as only 4 bits of the 8 data bits are read? This is really turning my head.

patriques
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  • It just means that ram can only transfer 4 bits per bus clock cycle, and rom can transfer 8, and you should take this into account when designing your control logic...? Am I missing a deeper question? Or maybe if you assume that a data word is transferred in one bus cycle, then you can see that ram data words are necessarily half the size of rom data words, which could cause problems... –  Sep 27 '12 at 06:51
  • I've removed the ´homework´ tag, as [it is deprecated](http://meta.stackexchange.com/questions/147100/the-homework-tag-is-now-officially-deprecated?cb=1) – J.A.I.L. Sep 27 '12 at 06:58
  • well no that kind of explains it, but then the deeper question is: does it mean that to take a full word into the register (if the word size is one byte) takes two clock cycles for the ram, and can be done in one clock cycle for the rom? If that's the case it's simpler than i thought it was, but how do you design the control logic to handle that and distinguish between the two? – patriques Sep 27 '12 at 14:31

1 Answers1

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You use two RAM parts side by side.

One provides D0-3 and the other D4-7.

Look at a DIMM module form a modern computer; there are many RAM chips, but they are in parallel.

Back in the old days, DRAM chips were all 1 bit wide so you needed really large numbers of them to make a memory bank. Apple II Schematic

Does this makes you winder about the RAM chips operating at the same speed ?

Issues with synchronization of RAM at increasing speeds led to the invention of SDRAM (Synchronous RAM) with the state machine in the RAM clocked by the CPU.

Just feel lucky that your assignment doesn't have RAM more like a DRAM with Row and Column addressing instead of an address bus.

Tim Williscroft
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