Makefile include file for same targets

Asked Sep 19 '12 at 20:43

Active Sep 20 '12 at 06:46

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I have a large project using recursive Make. Almost all the Makefiles are the same though. I'm basically building all the object files into the same directory like this:

$(OBJ)/%.o: %.c
        $(COMPILE) ${INCLUDES} -c $< -o $@

$(OBJ)/%.o: %.cpp
        ${CXX} ${INCLUDES} ${FLAGS}  -c -fPIC $< -o $@

Is it possible to put these targets in an include file so I don't have to put the same lines in every Makefile?

include I've only used for shared variables and when I tested this using include it did not work.

edited Sep 20 '12 at 06:46

ronalchn

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asked Sep 19 '12 at 20:43

goj

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It should work with `include`. Can you elaborate? – Beta Sep 19 '12 at 22:07
oops you're right...it did work. Turns out some of the Makefiles were different slightly Thanks! – goj Sep 21 '12 at 00:20

Makefile include file for same targets

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