Can some one explain why the golden rule when writing VHDL is that the if-then-else statement must be in a process. Is it because inside the process, the statements are executed sequentially, while outside they're not.
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The simple answer is "because that's how the syntax of the language is"!
If you want to select from some options with code not in a process you can do:
sig <= a when sel = 1 else
b when sel = 2 else
default_value;
or
with sel select
sig <= a when 1,
b when 2,
default_value when others;
Martin Thompson
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The author is correct, it's like that because that's the way it is. If's outside of a process are simple decision trees (and-or select logic). However for completeness I would add that there is a form of IF that exists outside of a process, it's called GENERATE and works a bit like #ifdef .... #endif in C. – Jay M Sep 21 '12 at 16:11
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At first I thought I was severely hampered because of this when I wanted to make a small block that switched off several signals *outside* a process, but I learned you can use the `when - else` and still use multiple signals after the `when`. Such as `sig <= a when (OPCODE = "000" and EN = "1"` – krb686 Feb 04 '15 at 00:42
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I might be wrong, but I think the main reason that if statements need to be in a process is that an if statement can potentially assign to more than one signal, if you wanted to do the same thing outside of a process you would need to use more than one conditional signal assignment.
For example:
process(C0, C1, A, B, C) is
begin
if C0 = '1' then
F <= A;
G <= C;
elsif C1 = '1' then
F <= B;
G <= B;
else
F <= C;
G <= A;
end if;
end process;
The equivalent conditional signal assignments outside of the process would be:
F <= A when C0 = '1' else B when C1 = '1' else C;
G <= C when C0 = '1' else B when C1 = '1' else A;
Peter Bennett
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