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Currently, I've been involved in FPGA design techniques using Xilinix. While solving design problems, I repeatedly found the use of elseif and elsif in if-chain almost for similar statements.

elsif(clk'event and clk='1') then
                 pr_state<=nx_state;

and

elseif S1=’0’ and  S0=’1’ then
     Z <= B;

My problem is- what's the difference between these two constructs? Are they similar? I've gone through D.L. Perry's VHDL book and other online VHDL tutorials' sites but can't find solution.Thanks in advance!

Jivan
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    I don't know VHDL and I guess there's no difference. It would be extremely confusing if they were one. I can't imagine a language designer doing this. – bokan Sep 02 '12 at 12:40
  • Well, I think there should be at least a point of difference, otherwise the designer would not make two constructs for exactly the same function. @bokan – Jivan Sep 02 '12 at 13:45
  • There are often synonyms or several ways to write the same thing in programming language. – bokan Sep 02 '12 at 14:01

2 Answers2

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As you can see here
http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html
elseif is not a valid keyword in vhdl. So if it is recognized, then some tool vendor wanted to do you a favour... I would guess that you actually saw else if, as pointed out above

BennyBarns
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It looks like the correct syntax is elsif. There's no mention of elseif in any VHDL reference. http://www.eda.org/rassp/vhdl/guidelines/vhdlqrc.pdf
http://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.html
http://www.lsi.die.upm.es/~angelfh/LCSE/docs/Synario_VHDL_Reference_Manual_1997.pdf

bokan
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  • Fun to see that this question is already referenced in google for the words "VHDL elseif elsif"... just one hour after. – bokan Sep 02 '12 at 14:04
  • Thanks for you effort. But, I've seen these two constructs in many famous writers' VHDL books. @bokan – Jivan Sep 02 '12 at 14:10
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    I think you saw "else if" not "elseif". "else if" is a else folowed by sequence. This sequence could be one instruction ...; or a bloc {} think of the following if(){} as one sequence. Anyways it's the same for sure. You should take this for granted and use your brain cycles for something else. – bokan Sep 02 '12 at 14:21
  • I don't think there is a space between ELSE and IF in this statement: ELSEIF (clear = ‘1’) THEN dout <= ‘0’; @bokan – Jivan Sep 02 '12 at 14:28
  • You told me you saw this in books, so I thought you had typed the example yourself. Do you have any reason to think they are different ? Do you need to use elseif ? Does it compile with both ? Does the program behave differently ? – bokan Sep 02 '12 at 14:38
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    Well, both of them get compiled and for this time the result is the same.As you have commented in your first comment 'I don't know VHDL' ,so it would be better to know that in VHDL, instructions are related to machine cycles and a designer should be aware of those so that he/she can optimize the design. Thinking so I have posted this question, perhaps there may be such reason. Finally, your efforts for my question are awesome, thanks! @bokan – Jivan Sep 02 '12 at 14:59
  • let us [continue this discussion in chat](http://chat.stackoverflow.com/rooms/16157/discussion-between-zane-and-bokan) – Jivan Sep 02 '12 at 15:02