3

When I run "cat /proc/interrupts", I can get the following:

           CPU0       CPU1
  0:        253       1878   IO-APIC-edge      timer
  1:          3          0   IO-APIC-edge      i8042
  7:          1          0   IO-APIC-edge      parport0
  8:          0          1   IO-APIC-edge      rtc0
  9:          0          0   IO-APIC-fasteoi   acpi
 12:          1          3   IO-APIC-edge      i8042
 16:     681584         60   IO-APIC-fasteoi   uhci_hcd:usb3, nvidia
 17:          0          0   IO-APIC-fasteoi   uhci_hcd:usb4, uhci_hcd:usb7
 18:          0          0   IO-APIC-fasteoi   uhci_hcd:usb8
 22:          2          1   IO-APIC-fasteoi   ehci_hcd:usb1, uhci_hcd:usb5
 23:         17         17   IO-APIC-fasteoi   ehci_hcd:usb2, uhci_hcd:usb6
 44:     146232     472747   PCI-MSI-edge      ahci
 45:        118        115   PCI-MSI-edge      snd_hda_intel
 46:   10038650        842   PCI-MSI-edge      eth1
NMI:      44479      43798   Non-maskable interrupts
LOC:   19025635   29426776   Local timer interrupts
SPU:          0          0   Spurious interrupts
PMI:      44479      43798   Performance monitoring interrupts
IWI:          0          0   IRQ work interrupts
RES: 3442001789 3442627214   Rescheduling interrupts
CAL:       1406       1438   Function call interrupts
TLB:     781318     792403   TLB shootdowns
TRM:          0          0   Thermal event interrupts
THR:          0          0   Threshold APIC interrupts
MCE:          0          0   Machine check exceptions
MCP:       2063       2063   Machine check polls
ERR:          0
MIS:          0

How can I get the interrupt number of "NMI" "LOC" "SPU" "PMI", etc.

dagelf
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Sean
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  • I want to know the vector of PMI. I am doing is first identifying PMI in VMM, then inject it into guest. – Sean Jul 08 '12 at 05:16

1 Answers1

7

On x86 NMIs are always on interrupt vector 2. The number is hard-coded just as common exceptions (division by 0, page fault, etc). You can find this in the CPU documentation from Intel/AMD.

If the APIC is enabled (as is the case in the dump presented in the question), Spurious Interrupt's interrupt vector number can be obtained from APIC's SVR register. Again, see the same CPU documentation on that.

If the APIC isn't enabled and instead the PIC is being used, then Spurious Interrupts are delivered as IRQ7 (see the 8259A PIC chip spec for that). The BIOS programs the PIC in such a way that IRQ7 is interrupt vector 0Fh, but Windows and Linux change this mapping to avoid sharing the same interrupt vectors for IRQs and CPU exceptions. It seems like this mapping can't be queried from the PIC, but it's established via sending the Initialization Control Word 2 (ICW2) to the PIC. Here's the relevant piece of Linux code in init_8259A():

    /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
       to 0x20-0x27 on i386 */
    outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);

That should answer the Spurious Interrupt vector part.

As for LOC and PMI, I think, these are local APIC's interrupts and you can find their interrupt vectors from the APIC just like with the Spurious Interrupt above.

Alexey Frunze
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  • Thanks for your response. The one I am looking for is the number of PMI. I just generalize the problem. I can found some of them, including NMI, are hard coded in the header file, but not PMI. And that is why am asking and see if someone konw how to check it out. PMI should be an APIC interrupt. Do you know how to check the interrupt vectors from the APIC? – Sean Jul 08 '12 at 05:22
  • Read the CPU documentation. It says where the APIC registers are and you should be able to read from them (provided, your code is running in the kernel or there's a way to read physical memory from a regular application with sufficient privileges). – Alexey Frunze Jul 08 '12 at 05:24
  • OK. I need to get interrupt vectors. I can see if one of the APIC register saves this information. – Sean Jul 08 '12 at 05:39
  • Looks like `LVT Timer register` and `LVT Performance Monitoring register` are the ones to read. – Alexey Frunze Jul 08 '12 at 05:48
  • Thanks. Do you know where to find the layout and other details of these registers? – Sean Jul 08 '12 at 06:24
  • Man... [http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html). – Alexey Frunze Jul 08 '12 at 06:35
  • In the Figure 10-8 of Intel SDM, it shows Performance Mon. Counters is using a vector. – wangt13 Aug 26 '20 at 07:51