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I'm working on a VHDL project for a Xilinx FPGA, and found myself at a cross road.

I need for example to add two signals (C=A+B), and found that Xilinx has Tool that can generate a component which will do the job.

But this could also be implemented in standard VHDL: C <= A + B

If I use standard VHDL the code should be portable, but does this has lower throughput?

I mean, does the special components use DSP functions inside the FPGA ect., that makes them faster, or can the Synthesizer normally handle this?

JakobJ
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  • What specific Xilinx component that "can do the job" are you referencing? – Josh Jun 27 '12 at 12:05
  • You'd better write **worst timing** than **lower throughput**. – wap26 Jun 28 '12 at 09:12
  • @wap26 Well, they are related right? If your timing is worse, your Fmax is lower, and so is your throughput. – Josh Jun 28 '12 at 09:51
  • @Josh Yes but the throughput is a higher-level concept to me. The throughput is related to your whole system, not to just an operator or a logic cell. Eg if you have a timing critical path elsewhere then this critical one will determine your Fmax and the throughput ; then the timing of your `+` operator may not impact the throughput, even if its timing gets better/worse. In addition, you can still define what is the throughput of a synchronous component if you want to, but for combinational logic (as the `+`) it does not make sense... Agreed, this is of rather low importance! – wap26 Jun 28 '12 at 12:08

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Any time you can infer something do so.

Performance is very rarely impacted, especially in the case of simple things like adders and multipliers. Even RAM blocks are easy to infer for many purposes - I only tend to instantiate vendor components if I need a very specific vendor-block behaviour.

The DSP blocks will be used well if you write VHDL code for adders and multipliers of the appropriate widths (or smaller) with pipelining that matches what is available inside the block. If you want to be more advanced and use (for example) Xilinx's DSP block's opcode input then you will have to instantiate a block.

Martin Thompson
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