Signal or variable counter inside a generate statement

Question

I have a problem with a generate statement. I'm generating a pipeline architecture, the basic problem is that I need another counter or variable besides the for index:

architecture behav of blockPipelineCordic is
    constant total: integer := stepNumber + stepNumber/pipeStep;
    signal signVector: std_logic_vector( (stepNumber - 1) downto 0);
    signal lx: std_logic_vector( ((total + 1)*dataSize - 1) downto 0);
    signal ly: std_logic_vector( ((total + 1)*dataSize - 1) downto 0);
    signal signCounter: integer := stepNumber - 1;
begin

stepGen:
for i in (total - 1) downto 0 generate
    begin

      signCounter <= signCounter - 1 when ((total - i) mod (pipeStep + 1) /= 0) else signCounter;

        stepGen0: if( (total - i) mod (pipeStep + 1) /= 0 ) generate
        begin U1: entity work.cordicStep(behav)
        generic map ((totalStepNumber - 1) - i,dataSize)
        port map(signVector(signCounter),lx(((i+2)*dataSize-1) downto (i+1)*dataSize),ly(((i+2)*dataSize-1) downto (i+1)*dataSize),lx(((i+1)*dataSize-1) downto i*dataSize),ly(((i+1)*dataSize-1) downto i*dataSize));
        end generate stepGen0;

        stepGen1: if( (total - i) mod (pipeStep + 1) = 0 ) generate
        begin U2: entity work.registerModule(behav)
        generic map (dataSize)
        port map(clk,lx(((i+2)*dataSize-1) downto (i+1)*dataSize),lx(((i+1)*dataSize-1) downto i*dataSize));
        end generate stepGen1;

        stepGen2: if( (total - i) mod (pipeStep + 1) = 0 ) generate
        begin U3: entity work.registerModule(behav)
        generic map (dataSize)
        port map(clk,ly(((i+2)*dataSize-1) downto (i+1)*dataSize),ly(((i+1)*dataSize-1) downto i*dataSize));
        end generate stepGen2;

end generate stepGen;
. . .

In the generation of the first structure I need to use a different index to signVector, I created a signal to be used as a counter (port map(signVector(signCounter),lx(((i+2)*dataSize-1) downto ) but it cannot be used as an index the error is: "Actual (indexed name) for formal "sub" is not a static signal name."

Any help would be appreciated :), ty

Your `signCounter` is assigned `total` times ! Remeber that all `<=` are **concurrent** assignments. — wap26, Jun 27 '12 at 09:08

Martin Thompson · Answer 1 · 2012-06-27T12:49:32.020

1

Sorry, you can't use an intermediate signal like that.

You could write a function, which given a value i will return the correct signCounter, without needing to store intermediate values.

You could try declaring the signal within the generate, but I don't think it'll get you what you want (the signal will end up with total number of drivers on it, rather than having several different values during the loop.) Generate is for "making static things", not dynamic things.

edited Jun 27 '12 at 12:49

answered Jun 26 '12 at 09:10

Martin Thompson

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Right. In your code, `signCounter` is assigned `total` times ! plus the initialization. @Martin: yes, a signal in the declarative part of the generate is ok. – wap26 Jun 27 '12 at 09:07
@wap26: Yes, I wasn't clear - it's allowed, but whether it provides the function... – Martin Thompson Jun 27 '12 at 12:46
Awesome, I didn't think about using functions, thank you so much, very useful answer. greetings – nexobios Jun 29 '12 at 21:24

score 0 · Answer 2 · answered Jun 26 '12 at 18:46

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While I have some issues following your code, it seems that signCounter is derivable from i. The math involved would be simpler to follow if you run the generate from 0 to total-1.

Alternatively try splitting it into two generate statements, the first from 0 to stepNumber - 1 that gerates your cordicSteps, and the second from 0 to total - 1 generating your registerModules.

Additionally you can combine stepGen1 and stepGen2

answered Jun 26 '12 at 18:46

Voider

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Sorry for the messy code still getting started in VHDL; and thanks I'll try to derive it from i, I didn't try because It was supposed to be a minor fix to the architecture and didn't wanted to make big changes to the code and I get lost easily with the bus sizes. Greetings – nexobios Jun 29 '12 at 21:31

Signal or variable counter inside a generate statement

2 Answers2