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I need to design a system that calculates correlation in verilog and I can only use fixed-point calculations with limited number of bits. So I need to implement a fixed-point multiplier which has less number of bits than the sum of the inputs (the inputs have the same length and number of fractional bits).

The point is that I can't just multiply them normally and then reduce the bits. So is there any particular way to do that?

bstpierre
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soroosh.strife
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  • How accurate do you need to be? Can you not round up your inputs and then multiply them using a fixed-point multiplier? Also, the width of the output of a multiplier should be sum of the widths of both inputs to get correct results, why this is not the case for you? – Ari Jun 13 '12 at 13:35
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    "The point is that I can't just multiply them normally and then reduce the bits" Why not? –  Jun 13 '12 at 14:56

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A=B*C works just fine - you have to keep track of where the binary point will be throughout your calculations. But that's just bookeeping.

If you want the compiler to do the bookkeeping for you, use VHDL and the standard (as of VHDL-2008) fixed_point package

Martin Thompson
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