5

I'm new to linux driver dev.

I'm writing helloworld driver.

here is the code:

#define MODULE
#define __KERNEL__
#include <module.h>
int init_module() 
{
 return 0;
}

void cleanup_module()
{
 return;
}

and here is makefile:

    CC=gcc
    MODFLAGS:= -O3 -Wall -DLINUX
    module.o: module.c
    $(CC) $(MODFLAGS) -c module.c

But when I run make command I have the following: makefile:3: * “commands commence before first target” error

whats wrong?

user1284151
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2 Answers2

8

Remove the leading tabs in the makefile, from every line that isn't a command:

CC=gcc
MODFLAGS:= -O3 -Wall -DLINUX
module.o: module.c
    $(CC) $(MODFLAGS) -c module.c
Beta
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2

Although this wasn't the case for you, I encountered the same error message with a different reason. So I am answering here as well so that it may aid people in the future when they encounter the error message but the reason isn't as obvious as in your case.

Here's a minimal example to provoke the error condition by merely having a file with an equal sign in its name match the $(wildcard) (obviously here for demonstration purposes I am matching only file names with a =). Strictly speaking it doesn't matter what method you use to retrieve the names for the $(FILES) variable.

FILES := $(wildcard ./*=*)

.PHONY: all

define foo
all: something-$(1)
something-$(1): $(1)
    cat $$^ > $$@
endef

$(foreach goal,$(sort $(FILES)),$(eval $(call foo,$(goal))))

The problem appears to be in the way the expansion happens - in this case and it will only happen due to the macro.

Anyway, I was stumped when I ended up with this error message while the make file itself - also according to version control - hadn't changed. Until it dawned on me that there must be some circumstantial reason for the problem then. May it help the future person in search for an answer.

0xC0000022L
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