The code above with the two loops under assumption of both counters initially set to zero takes 197119 cycles (instead of 196392) right?
I'm referring to the code:
- Delay_0 decfsz COUNT1
- goto Delay_0
- decfsz COUNT2
- goto Delay_0
The reason is that the inner loop associated with count1 will loop for 255 times, which means {255 times 3 instruction cycles} plus the final decfsz takes an extra 2 cycles. So for the very FIRST time that this inner loop cycles through, the associated delay (d1F) will be d1F = 255*3 + 2 = 767 cycles. This all happens before we even get to the decfsz for count2. Next up, the rest of the activity occurs when we reach decfsz count2; which begins with decfsz count2, followed by goto Delay_0, where the 'goto' will invoke another inner loop delay (equal to d1F). So this triple combination consisting of decfsz count2, goto Delay_0, and d1F will be associated with a count2 index value of 255. We then keep getting more triple combos...with index 254, then index 253...all the way down to count2 index of 1. So this means we get 255 triple combinations. And lastly, we then terminate with the final decfsz count2 (with index 0). The final decfsz count2 'instruction' takes 2 cycles instead of 1. So the second portion of the delay is then (d1F+3)*255 + 2. The '3' (instruction cycles) is due to decfsz plus goto instructions during normal looping.
So when we put the first and second portions of the delay together, we get:
- d2F = d1F + (d1F+3)x255 + 2 = 767 + (767+3)x255 + 2 = 197119
Now if we have multiple loops, then we can use equations:
- d(n)_F = d(n-1)_F + {d(n-1)_F + 3}x255 + 2 = 256xd(n-1)_F + 767
and
- d(n)_C = d(n-1)_C + {d(n-1)_F + 3}x{count_n - 1} + 2
where the 'F' in d(n)_F or d(n-1)_F denotes a condition where all counters are initialized with ZERO value. And 'C' in d(n)_C denotes a condition where the counter for the nth loop is initialized with whatever value we had initially chosen. And 'n' is associated with the nth loop. And 'n-1' is associated with the (n-1)th loop.
So if we have 2 loops, then d(1)_F is the delay due to loop #1 with 'Full' number of cycles (ie.. counter1 is initially ZERO or 256); and d(2)_F is the delay due to loop #1 AND loop #2 for the case when both counter1 and counter2 are initially equal to ZERO or 256.
- d(1)_C is the delay due to loop #1 for the case where count1 is initialized with whatever value we had initially chosen.
- d(2)_C is the delay due to loop #1 AND loop #2 for the case where count2 is initialized with whatever value we had initially chosen.
Note that count_n is the INITIAL counter value for the nth loop.
Also, if a particular counter is initially initialized with a ZERO value, then it is often convenient to treat that value as being '256'. This is for an EIGHT bit counter of course. For example, if count1 = 0, it is convenient to treat it as being count1 = 256 (instead of 0).
- We can also define: d(0)_F = 0, and d(0)_C = 0.
So for a 3 loop system with count1 = 1, count2 = 4, and count3 = 2,
d(1)_F = 256xd(0)_F + 767 = 256x0 + 767 = 767
d(1)_C = 0 + {0 + 3}x{1 - 1} + 2 = 2
d(2)_F = 256xd(1)_F + 767 = 256x767 + 767 = 197119
d(2)_C = d(1)_C + {d(1)_F + 3}x{4 - 1} + 2 = 2 + {767+3}x3 + 2 = 2314
d(3)_F = 256xd(2)_F + 767 = 256x197119 + 767 = 50463231
d(3)_C = d(2)_C + {d(2)_F + 3}x{2 - 1} + 2 = 199438
The 3 loop system is like:
- Delay_0 decfsz count1
- goto Delay_0
- decfsz count2
- goto Delay_0
- decfsz count3
- goto Delay_0
Kenny Leong