Verilog reg assignment to part of another reg

Question

I am using Verilog with modelSim and I get the following errors when I try to assign reg variables to different parts of another reg variable:

** Error: Range width must be greater than zero.
** Error: Range width must be constant expression.

here is the relevant code:

 integer f; //zd, qd, R and Q are regs

    always @ * begin 
    f = 52 - zd; 
    R = qd[f +:0]; 
    Q = qd[63 -:f+1]; 
    end

I want R to include qd (from 0 to f) and Q to be (the rest) qd (from f+1 to 63). How to do it? Thanks.

Here is [an answer](http://stackoverflow.com/questions/7543592/verilog-barrel-shifter/7543745#7543745) to a similar problem. — , Apr 09 '12 at 14:27

score 4 · Accepted Answer · answered Apr 06 '12 at 17:01

4

What you are trying to do is not legal in verilog 2001.

As your warning says, Range width must be constant expression, i.e. you cannot have variable length part selects.

You can have fixed length part select that varies the starting point (i.e. select 8 bits starting from f), but the syntax for that is this:

vector_name[starting_bit_number +: part_select_width]
vector_name[starting_bit_number -: part_select_width]

In hardware the size of a bus must be a fixed size, you cannot change the number of wires in silicon based on the contents of a register :)

answered Apr 06 '12 at 17:01

Tim

That true but does not achieve what I really wanted. What if the part select_width is greater than the remaining bits? all of the remaining bits will be selected with no problem? – mj1261829 Apr 07 '12 at 05:18
@user1261829 : It would probably just generate invalid data if you selected the starting bit to be such that the part select would overflow the bus. Can you describe what you're trying to do at a higher conceptual level? Maybe there is a better way to go about it than what you're trying to do. – Tim Apr 07 '12 at 07:37
Actually, qd is the result of multiplying 2 fixed-point numbers after their conversion from floating point and I want the result to be splitted into integer bits and fractional bits. – mj1261829 Apr 07 '12 at 08:29

1 Answers1