0

How much time does the CPU wait to go to higher mode, let's say from C0 to C1? Or if it can be customized, where can I find the current value?

Also, does the the C-State changes in stages like first go to C1 mode then wait there for some time, and go to C2 etc. It seems so as it's the only possible way to go to all C-State modes. Otherwise, there is no reason to have intermediate C-State modes.

Also if you can answer this too: What does the following C-State output mean?

Community
  • 1
GP92
  • 681
  • 2
  • 9
  • 27

1 Answers1

0

According to http://ena-hpc.org/2014/pdf/paper_06.pdf and https://books.google.co.uk/books?id=DFAnCgAAQBAJ&pg=PA177&lpg=PA177&dq=c+state+latency+MSR&source=bl&ots=NLTLrtN4JJ&sig=1ReyBgj1Ej0_m6r6O8wShEtK4FU&hl=en&sa=X&redir_esc=y#v=onepage&q=c%20state%20latency%20MSR&f=false you may be able to fish x86 C-state entry and exit latencies out of ACPI but it's unclear how accurate this information is. Looking at https://lwn.net/Articles/658461/ suggests ARM machines may encode this information via DeviceTree. http://connect.linaro.org.s3.amazonaws.com/hkg18/presentations/hkg18-111.pdf gives an experimental method for trying determine entry and exit states using an ARM board.

Note: this is very low level information - if you're not a kernel developer you're probably more concerned with how much residency you're spending in each C-state rather than what the entry and exit latencies of each C-state are...

Anon
  • 1,245
  • 10
  • 23