This is all manufacturer and device-specific. In some cases, it's even firwmare / OS specific.
Devices that move packets around (Ethernet switches moving Ethernet frames, IP routers moving IP datagrams, ATM switches moving cells) try to do so in the most efficient manner possible. This often means using custom chips (ASICs) with hardware-based algorithms to identify traffic flows and move them.
Often, the features of these hardware-based algorithms are limited (often with respect to policy-based traffic flow manipulation-- security, deep packet inspection, etc) and, when more advanced decision-making is necessary the ASICs will need to involve the device's CPU and firmware to make flow decisions.
Using the CPU and software to make the flow decision is generally much slower than a hardware-only path. In some devices, the CPU can make the decision for the initial packet, and will make an entry into a RAM-based table that the ASICs have access to so that future packets in the same flow can follow a hardware-only path.
Maufacturers aren't going to make the implementation details of their algorithms public because this is typically their "secret sauce" that helps to differentiate their gear in the marketplace. Further, these algorithms are typically dependent on features of the ASICs and underlying hardware that the devices are built upon.
You can infer, by reading up on protocols and learning HOW a packet should flow inside a switching / routing device. What the specific algorithms and optimizations are for a given device, though, aren't typically accessible to you.