Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog has been officially part of the SystemVerilog language. The current version is IEEE standard 1800-2023.
| Paradigm | Structured |
|---|---|
| Designed by | Prabhu Goel, Phil Moorby and Chi-Lai Huang |
| Developer | IEEE |
| First appeared | 1984 |
| Stable release | IEEE 1800-2023
/ 6 December 2023 |
| Typing discipline | Static, weak |
| Filename extensions | .v, .vh |
| Website | https://ieeexplore.ieee.org/document/5985443 |
| Dialects | |
| Verilog-AMS | |
| Influenced by | |
| Pascal, Ada, C, Fortran | |
| Influenced | |
| SystemVerilog | |
| |
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