Teraflops Research Chip

Intel Teraflops Research Chip (codenamed Polaris) is a research manycore processor containing 80 cores, using a network-on-chip architecture, developed by Intel's Tera-Scale Computing Research Program. It was manufactured using a 65 nm CMOS process with eight layers of copper interconnect and contains 100 million transistors on a 275 mm² die. Its design goal was to demonstrate a modular architecture capable of a sustained performance of 1.0 TFLOPS while dissipating less than 100 W. Research from the project was later incorporated into Xeon Phi. The technical lead of the project was Sriram R. Vangal.

The processor was initially presented at the Intel Developer Forum on September 26, 2006 and officially announced on February 11, 2007. A working chip was presented at the 2007 IEEE International Solid-State Circuits Conference, alongside technical specifications.