Cannon Lake (microprocessor)
Cannon Lake (formerly Skymont) is Intel's codename for the 10 nm die shrink of the Kaby Lake microarchitecture. As a die shrink, Cannon Lake is a new process in Intel's process-architecture-optimization execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the AVX-512 instruction set.
| General information | |
|---|---|
| Launched | May 15, 2018 |
| Discontinued | February 28, 2020 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer(s) |
|
| Performance | |
| Max. CPU clock rate | 3.2 GHz |
| Cache | |
| L1 cache | 64 KB per core |
| L2 cache | 256 KB per core |
| L3 cache | 2 MB per core |
| Architecture and classification | |
| Technology node | Intel 10 nm (tri-gate) transistors |
| Microarchitecture | Palm Cove |
| Instruction set | x86-64 |
| Instructions | x86-64, Intel 64 |
| Extensions | |
| Physical specifications | |
| Cores |
|
| GPU(s) | Factory disabled |
| Socket(s) |
|
| Products, models, variants | |
| Product code name(s) |
|
| Brand name(s) | |
| History | |
| Predecessor(s) | Desktop: Coffee Lake (2nd optimization) Kaby Lake Refresh (2nd optimization) |
| Successor(s) | Ice Lake (architecture) |
| Support status | |
| Legacy support for iGPU | |
Prior to Cannon Lake's launch, Intel launched another 14 nm process refinement with the codename Coffee Lake.
The successor of Cannon Lake is Ice Lake, powered by the Sunny Cove microarchitecture, which represents the architecture phase in the process-architecture-optimization model.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.