Project Denver
Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
| General information | |
|---|---|
| Launched | 2014 (Denver) 2016 (Denver 2) |
| Designed by | Nvidia |
| Cache | |
| L1 cache | 192 KiB per core (128 KiB I-cache with parity, 64 KiB D-cache with ECC) |
| L2 cache | 2 MiB @ 2 cores |
| Architecture and classification | |
| Technology node | 28 nm (Denver 1) to 16 nm (Denver 2) |
| Instruction set | ARMv8-A |
| Physical specifications | |
| Cores |
|
| General information | |
|---|---|
| Launched | 2018 |
| Designed by | Nvidia |
| Max. CPU clock rate | to 2.3 GHz |
| Cache | |
| L1 cache | 192 KiB per core (128 KiB I-cache with parity, 64 KiB D-cache with ECC) |
| L2 cache | 2 MiB @ 2 cores |
| L3 cache | (4 MiB @ 8 cores, T194) |
| Architecture and classification | |
| Technology node | 12 nm |
| Instruction set | ARMv8.2-A |
| Physical specifications | |
| Cores |
|
Project Denver is targeted at mobile computers, personal computers, servers, as well as supercomputers. Respective cores have found integration in the Tegra SoC series from Nvidia. Initially Denver cores was designed for the 28 nm process node (Tegra model T132 aka "Tegra K1"). Denver 2 was an improved design that built for the smaller, more efficient 16 nm node. (Tegra model T186 aka "Tegra X2").
In 2018, Nvidia released an improved design (codename: "Carmel", based on ARMv8 (64-bit; variant: ARM-v8.2 with 10-way superscalar, functional safety, dual execution, parity & ECC) got integrated into the Tegra Xavier SoC offering a total of 8 cores (or 4 dual-core pairs). The Carmel CPU core supports full Advanced SIMD (ARM NEON), VFP (Vector Floating Point), and ARMv8.2-FP16. First published testings of Carmel cores integrated in the Jetson AGX development kit by third party experts took place in September 2018 and indicated a noticeably increased performance as should expected for this real world physical manifestation compared to predecessors systems, despite all doubts the used quickness of such a test setup in general an in particular implies. The Carmel design can be found in the Tegra model T194 ("Tegra Xavier") that is designed with a 12 nm structure size.