Xeon Phi
Xeon Phi was a series of x86 manycore processors designed and made by Intel. It was intended for use in supercomputers, servers, and high-end workstations. Its architecture allowed use of standard programming languages and application programming interfaces (APIs) such as OpenMP.
Xeon Phi 5100 without heatsink | |
| General information | |
|---|---|
| Launched | 2010 |
| Discontinued | 2020 |
| Marketed by | Intel |
| Designed by | Intel |
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| Performance | |
| Max. CPU clock rate | 1.053 GHz to 1.7 GHz |
| Cache | |
| L1 cache | 32 KB per core |
| L2 cache | 512 KB per core |
| Architecture and classification | |
| Application | Supercomputers High-performance computing |
| Technology node | 45 nm transistors to 14 nm transistors (tri-gate) |
| Microarchitecture | Larrabee |
| Instruction set | x86-32, x86-64 |
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| Memory (RAM) |
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| Socket(s) | |
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Xeon Phi launched in 2010. Since it was originally based on an earlier GPU design (codenamed "Larrabee") by Intel that was cancelled in 2009, it shared application areas with GPUs. The main difference between Xeon Phi and a GPGPU like Nvidia Tesla was that Xeon Phi, with an x86-compatible core, could, with less modification, run software that was originally targeted to a standard x86 CPU.
Initially in the form of PCI Express-based add-on cards, a second-generation product, codenamed Knights Landing, was announced in June 2013. These second-generation chips could be used as a standalone CPU, rather than just as an add-in card.
In June 2013, the Tianhe-2 supercomputer at the National Supercomputer Center in Guangzhou (NSCC-GZ) was announced as the world's fastest supercomputer (as of June 2023, it is No. 10). It used Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon E5 v2 processors to achieve 33.86 petaFLOPS.
The Xeon Phi product line directly competed with Nvidia's Tesla and AMD Radeon Instinct lines of deep learning and GPGPU cards. It was discontinued due to a lack of demand and Intel's problems with its 10nm node.