P6 (microarchitecture)

P6
	Die shot of Deschutes core
General information
Launched	November 1, 1995
Performance
Max. CPU clock rate	150 MHz to 1.40 GHz
FSB speeds	66 MHz to 133 MHz
Cache
L1 cache	Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache); Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache)
L2 cache	128 KB to 512 KB; 256 KB to 2048 KB (Xeon)
Architecture and classification
Microarchitecture	P6
Instruction set	x86-16, x86-32
Extensions	MMX (Pentium II/III); SSE (Pentium III);
Physical specifications
Transistors	5.5M 500 nm; 7.5M 350 nm; 7.5M 250 nm (B0, B1); 9.5M 250 nm (B0, C0); 19M 250 nm (B0); 28M 180 nm (A1, A2, B0, C0, D0); 44M 130 nm (A1, B1, C1, D0);
Cores	1;
Socket(s)	Socket 8; Slot 1; Socket 370; Socket 479;
Products, models, variants
Model(s)	Celeron Series; Pentium II Series; Pentium III Series; Pentium Pro Series; Pentium II Xeon Series; Pentium III Xeon Series;
Variant(s)	Pentium M; Enhanced Pentium M;
History
Predecessor(s)	P5
Successor(s)	NetBurst, Pentium M
Support status
	Unsupported

The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686. It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.

P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).

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