eSi-RISC
eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.
| Designer | eSi-RISC |
|---|---|
| Bits | 16-bit/32-bit |
| Introduced | 2009 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Intermixed 16 and 32-bit |
| Branching | Compare and branch and condition code |
| Endianness | Big or little |
| Extensions | User-defined instructions |
| Registers | |
| 8/16/32 General Purpose, 8/16/32 Vector | |
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