Xtensa is a customizable 32-bit RISC ISA found in Tensilica's Xtensa chips, mostly used as DSPs. (Now owned by Cadence). Use [esp32] or [esp8266] for questions about their SDKs.
Use this tag for questions about the Xtensa ISA, assembly language, or Xtensa-specific C/C++ intrinsics.
Use esp32 or esp8266 for questions about their SDKs (like problems compiling with their headers or linking with their libraries).
See https://en.wikipedia.org/wiki/Tensilica
The Xtensa instruction set is a 32-bit architecture with a compact 16- and 24-bit instruction set. The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers
The Xtensa architecture offers a user-customizable instruction set through automated customization tools that can extend the Xtensa base instruction set, including SIMD instructions, new register files.
Wikipedia also adds that specific Xtensa chips range from low-power cacheless microcontrollers to "16-way SIMD processors, 3-issue VLIW DSP cores" or "1 TMAC/sec neural network processors" (multiply-accumulate)
Related tag: cadence is the company that now owns Tensilica and their Xtensa architecture. https://ip.cadence.com/. Use [cadence] for questions about the toolchain it provides. (Editor's note: I think that's accurate usage guidance, but not sure.)
Specific hardware / boards using Xtensa-ISA CPUs include many things outside the CPU, and have dev tools, SDKs, and so on which are totally specific to them, not the Xtensa ISA. Those are often C/C++ and toolchain questions specific to that one board and vendor-supplied files, not Xtensa chips in general.
- esp32 Bluetooth / WiFi ESP32 hardware and dev-tools issues.
- esp8266 WiFi chip. See also https://github.com/esp8266/Arduino
Resources
ISA ref manual: https://0x04.net/~mwk/doc/xtensa.pdf
GCC Xtensa options: (https://gcc.gnu.org/onlinedocs/gcc/Xtensa-Options.html).
https://en.wikipedia.org/wiki/Tensilica_Instruction_Extension can customize Xtensa cores. (At design time, not runtime). Extensibility is the literal namesake of Xtensa.
Slides from 2000 from Earl Killian, Tensilica's the lead architect for Xtensa: http://bwrcs.eecs.berkeley.edu/Classes/CS252/Notes/xtensa_022400.pdf including 1. How Tensilica and Xtensa came to be, 2. What Xtensa is, with motivation for the decisions we made
