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Questions tagged [x86-64]

x86-64 is a 64 bit extension to the Intel x86 architecture

x86-64 is a 64 bit instruction set, backwards compatible with the 16 and 32 bit architectures originating from the Intel 8086 processor. It is sometimes known as amd64 (common in GNU/Linux) or x64 (usually only seen in Windows).

The specification was created by AMD, and has been implemented by AMD, Intel, VIA, and others.

See the x86 tag for programming and optimising guides and other resources.

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How would I translate the following assembly code from the compiler to C when working with structs?

Suppose I define a new struct: struct s { int *x; struct { short sh[2]; int i; } w; struct s *next; }; In addition, I write a function to initialize it: void init_s(struct s *ss) { ss->w.sh[1] = /* Line 1 */; ss->x =…
John Issacs
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Out-of-order execution in C#

I have the following snippet: static long F(long a, long b, long c, long d) { return a + b + c + d; } which generates: $.<
$>g__F|0_0(Int64, Int64, Int64, Int64) L0000: add rdx, rcx L0003: lea rax, [rdx+r8] L0007: add…
user12722843
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Windows object file COFF relocations explanation

I'm trying to create an x86-64 Windows COFF object file, but I don't entirely understand the different types of relocations described at https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#x64-processors. Specifically, I'm not sure what…
abel1502
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x86-64 Kernel crashing on setting up the IDT

I am currently trying to create an x86-64 Kernel from scratch (using GRUB Multiboot2 as a bootloader). I set up my GDT just fine, but when setting up my IDT, there seems to be a problem. I isolated the issue to be my call of lidt by hlting before…
Hacked
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x86_64 check if power of 2 load / store will page cross for 2 pointers

Basically I am looking to implement the following in x86_64 assembly as fast as possible. (Where foo and bar may be something like glibc's hand-written asm strcpy or strcmp, and we want to start out with wide vectors but without the safety and/or…
Noah
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How do AMD64 page entry base address fields encode a 52-bit address in 40 bits?

I'm trying to manually walk the paging structures in order to convert a virtual address into its physical address. I have a question about the physical base address fields stored in the PML4E, PDPE, PDE, and PTE. The page size on my system is 4KB.…
Arush Agarampur
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Debugging NASM local labels with gdb

I have been having some issues debugging code assembled by nasm with gdb: it seems like gdb doesn't do well with nasm local labels. nasm generates a local symbol named «function».label, which seems to confuse gdb, as it loses track of which function…
Marco
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Is that possible to set interrupt that breaks when cpu write to an specific address?

Is it possible to make x86 cpu interrupt when specific address is being written? I want a hardware mechanism to monitor some address's changing.
Shore
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How to encode an instruction when we just know the hex for opcode

In this source, they have given that hex for cmp r/m16/32 imm8 is 0x837. Somewhere i got that, hex for ebp is 0b0101. With this information, how can i encode the instruction cmp dword [ebp-4] 2? I have been searching for this from a couple of hours…
Sourav Kannantha B
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How to reverse R_X86_64_JUMP_SLOT relocations?

I am building an ELF binary which needs to be able to process and reverse its own relocations at runtime. (The reversing will happen in a separate buffer, not in the original code page, obviously.) The purpose of this is so that the module contents…
Mitch Lindgren
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Why does multiple class member assignments produce redundant assembly?

While playing with C# I came across to this "strange behavior". The function public static Vec3 f() { var v = new Vec3(); v.x = 0; v.y = 0; v.z = 0; v.x = 0; v.y = 0; v.z = 0; v.x = 0; v.y = 0; v.z = 0; …
user12722843
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Conditional jump to memory address

Is something like the following possible? cmp $3, %rdi jz (%r11) file.s:52: Error: operand type mismatch for `jz' Or: Warning: indirect jmp without `*' Or do you have to jump 'through' a label which can then do the jmp %r11. Or how does that…
samuelbrody1249
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Is there a reason why Roslyn does not optimize multiple increments?

I was trying to see how Roslyn optimizes the following snippet: code public int F(int n) { ++n; ++n; ++n; ++n; return n; } asm C.F(Int32) L0000: inc edx L0002: inc edx …
user12722843
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Why is Modulo 2 optimization different from x&1?

Why is the assembly output of this code: code int f(int n) { return n % 2; } asm f: mov edx, edi shr edx, 31 lea eax, [rdi+rdx] and eax, 1 sub eax, edx ret different from…
user12722843
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converting ASM instruction RDRand to Win64

I have this function (RDRand - written by David Heffernan) that seam to work ok in 32 bit, but failed in 64 bit : function TryRdRand(out Value: Cardinal): Boolean; {$IF defined(CPU64BITS)} asm .noframe {$else} asm {$ifend} db $0f db $c7 db…
zeus
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