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Questions tagged [tlb]

The translation lookaside buffer (TLB) enables modern CPUs to quickly map virtual memory addresses to physical memory addresses and vice versa. Operations that flush the TLB cause a performance hit until it is repopulated.

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1GB pages and Transparent Huge Pages (Linux)

The Transparent Huge Pages(THP) support in recent Linux kernels allows automatic promotion/demotion between different page sizes (e.g., 4KB and 2MB in x86-64). But I am not sure if THP can also promote/demote page sizes between 4KB and 1GB pages or…
Arka
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Linux Kernel Invalidating TLB Entries

In the linux kernel, I wrote code that resembles copy_page_range (mm/memory.c) so copy memory from one process to another with COW optimization. The destination and source addresses can be offset by PAGE_SIZE and COW still works. I noticed, however,…
Chris
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How to cause a TLB thrashing with a user process?

My current work needs to generate a specified number of TLB misses on CPU of Intel Core series, while it's not going on well. I've tried many methods but all of them have a very high rate of TLB hit. Does anyone know some useful information about…
uraj
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VIPT Cache: Connection between TLB & Cache?

I just want to clarify the concept and could find detail enough answers which can throw some light upon how everything actually works out in the hardware. Please provide any relevant details. In case of VIPT caches, the memory request is sent in…
Uchia Itachi
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Software prefetching across page boundary on x86

My understanding is that hardware prefetching will never cross page boundaries. I'm wondering if a software prefetch has the same restriction i.e. can I use a software prefetch to avoid a future TLB miss. From searching around, it appears to be…
jmetcalfe
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When L1 misses are a lot different than L2 accesses... TLB related?

I have been running some benchmarks on some algorithms and profiling their memory usage and efficiency (L1/L2/TLB accesses and misses), and some of the results are quite intriguing for me. Considering an inclusive cache hierarchy (L1 and L2…
nuno
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MIPS memory execution prevention

I'm doing some research with the MIPS architecture and was wondering how operating systems are implemented with the limited instructions and memory protection that mips offers. I'm specifically wondering about how an operating system would prevent…
Rebecca Couture
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Understanding TLB from CPUID results on Intel

I'm exploring leaf 0x02 of the cpuid instruction and came up with a few questions. There is a table in the documentation which describes what cpuid results mean for the TLB configuration. Here they are: case 1 56H TLB Data TLB0: 4 MByte pages, 4-way…
St.Antario
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How is the size of TLB in Intel's Sandy Bridge CPU determined?

The wiki webpage(https://en.wikipedia.org/wiki/Sandy_Bridge) mentioned that Data TLB has 64, 32 and 4 entries respectively for 4KB, 2MB and 1GB pages. I found these numbers hard to understand. Sandy Bridge has a virtual address of 48 bits, which…
Harper
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How to convert virtual address to physical address from user space? Three different methods gave different results in Linux kernel 4x version

First of all, I’m sorry for so long question. I do some simulation modeling task and I need to translate user space virtual address into kernel space physical addresses. I used three different method and got three different results. Could you please…
shs_sf
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TLB structure in intel

I started from Patterson & Hennessy book with basic definitions and then followed the intel programming reference documents for more information about TLB. From the intel documents i got to know the high level design of TLB. such as line size,…
77H3jjuu
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Updating page table when an entry is evicted from TLB

Is page table updated when an entry is evicted from TLB? and if so, why? what information is updated in the page table? I think updating page table is not needed when the evicted page is clean. Similarly, is page table updated when a page is cached…
aminfar
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Designing a virtual memory with TLB

I've been given the following problem and I'm not sure exactly how to approach it: Consider a virtual memory system with the following properties: · 35-bit virtual address · 16 KB pages · 32-bit physical address Assume that…
audiFanatic
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Command to measure TLB misses on LINUX

Could some one direct me to a command to measure TLB misses on LINUX, please? Is it okay to consider minor page faults as TLB misses?
samarasa
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Cache set-sizes that aren't a power of two

I've got a Linux computer with a Ryzen 7 1800X CPU. According to WikiChip it has a L2-DTLB of 1536 entries. So I assumed the associativity to be divisible by 3. I wrote a little program that checks the associativity reported by CPUID. Interestingly…
Bonita Montero
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