Questions tagged [thumb]

A reduced instruction set for ARM processors (based on a 16-bit encoding, instead of 32 bits in standard ARM mode), originally intended for embedded systems with a small amount of RAM. Also for question with the later Thumb2 mixed 16 and 32 bit instruction modes. Consider the tags 'slider' and 'thumbnails' for other meanings of 'thumb'.

This tag is for questions concerning the ARM CPU's operating mode called thumb. Questions about thumb assembly language, interworking between thumb and ARM mode as well as operating system issue in dealing with thumb mode are on topic.

The Thumb instruction set (16 bit only) with restricted use of r8-r15 was later extended to include a mix of 16 and 32 bit instructions. This was called Thumb-2. Thumb-2 is a marketing term. Different CPU families and even specific devices have different instructions. Thumb-2 is fairly meaningless in a technical sense (except it means variable length instructions (always two halfwords) are available along with 16 bit thumb instructions). Thumb-2 at wikipedia

On modern ARM CPUs, Thumb-2 is as rich as the traditional 32-bit mode and much more memory efficient.

For questions related to the scrollbar thumbs consider one of,

For questions about thumbnails, use the tag .

See also:

The paper Profile guided selection of ARM and thumb instructions gives some benchmarking of legacy thumb versus 32 bit modes. Different algorithms are faster in one mode versus the other. The paper is somewhat obsolete as Thumb-2 will be more efficient in modern (2014+) CPUs. Although some deeply embedded devices may only support Thumb.

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Can I force a Cortex-M4 ARM processor to use conditional instructions outside an IT block?

I need to profile different machine instruction for a project, so I'm running some instructions in a loop of ~200 instructions per time (using .rept in an __asm__ directive). The processor I'm using is an ARM Cortex-M4. I need now to test ARM's…
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ARM GCC + Cortex M4: Calling address as function generates BLX instead of BL

I build as little OS for a CortexM4 CPU which is able to receive compiled binaries over UART and schedule them dynamically. I want to use that feature to craft a testsuite which uploads test programs being able to directly call OS functions like…
wolfbiker1
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ARM7a instruction - there is no branch BX defined for an immediate (relative displacement), what is an alternative?

I'm modifying an assembler/linker to add an ARM7a backend. To interwork with a call (BL) there is BLX so if I see a global symbol with bit0 set I know to switch a BL to a BLX instruction. But for a branch there is no BX available for an immediate…
progman
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how arm-thumb instruction set's blx instruction support 4MB range

Read from https://www.keil.com/support/man/docs/armasm/armasm_dom1361289866046.htm that arm-thumb instruction's blx instruction can support maximum 4MB of jump range. But as far as I know, arm-thumb instruction is only 16 bits long, so how can 16…
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Assembling THUMB instrutions to execute on Cortex-M3

As an exercise, I want to let STM32F103 execute from internal SRAM. The idea is to write some THUMB assembly by hand, assemble it with arm-none-eabi-as, load the machine code into SRAM with OpenOCD's mwh instruction, set PC to the beginning of SRAM…
nalzok
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Apple AS and ARM/Thumb ADDS instruction

I'm working on an iPhone/iPad project, and I want to update the status register during some (not all) arithmetic operations. By default, Xcode uses 'Compile for Thumb' and I don't want to change it. The following GCC inline assembly code works fine…
jww
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Is it atomic to access(load/store) 32 bit integer when using ARM Thumb instruction set?

Using ARM cortex with thumb instruction set and Keil realview compiler, is it safe to access to 32 bit integer? Since the thumb register set is 16 bits, does this mean, fetching a 32 bit int needs 2 machine instructions? If so, accessing 32 bit…
Zhichao
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ARM parity of low 8 bits of a register

I have found a few difficulties with the assembly language and unfortunately when I search the google for information I can't find anything that helps me with my problem. I have written this code and I'm looking for help to see if there's a way to…
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UNALIGNED Usage Fault on LDR instruction-CortexM7

I am debugging an assembly code written for a CortexM7 target. Inside the busFault handler there is a LDR instruction which when executed causes a UNALIGNED Usage Fault and as a result a forced Hard Fault occurs. What I know is that by default there…
SS01
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How do I optimize a block copy and right shift + saturate to max=5, for Cortex-M3

Basically, I need to make this piece of code more efficient either by reducing the size of the overall code to reduce memory size or make it more efficient in how it runs. I am using Thumb 2 as well as the Cortex-M3. I have tried reducing the…
Hysteria103
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How do I reduce execution time and number of cycles for a factorial loop? And/or code-size?

Basically I'm having a hard time getting the execution time any lower than it is, as well as reducing the amount of clock cycles and memory size. Does anyone have any idea on how I can do this? The code works fine I just want to change it a…
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Simple example of Table Branch Byte (TBB) in arm thumb

I am trying to figure out the details of how TBB works in arm assembly. Im just trying to figure out a simple example but no matter what my code goes to infinite loop or doesn't compile. .syntax unified .thumb BranchTable_Byte: …
DarkLink
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Are ARM Cortex-M0 Stacking Registers Saved On $psp or $msp During Hardfault?

I have an issue where my Cortex-M0 is hard faulting, so I am trying to debug it. I am trying to print the contents of the ARM core registers that were pushed to the stack when the hard fault occurred. Here is my basic assembly…
cDreamer
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How does gdb know if printed instructions are in arm or thumb mode?

Let's say you're in a gdb session and you're printing instructions of libc functions via x/[num_of_instructions]i [address]. How does gdb know whether they are to be interpreted as thumb or arm instructions?
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Benchmarks on baremetal systems

I am using the LPC43xx series, which has cortex-m4/m0. This is a bare-metal system. I am new to bare metal programming and I want to make small benchmark programs for performance evaluation. This is a non-cache system. How can I do this ? or Should…
Kael
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