C++ library used for system-level modeling of hardware designs. Used by engineers in making architectural decisions, modeling performance and enabling software/firmware development concurrently with traditional hardware development.
Wiki
SystemC is a collection C++ classes and macros which provide an event-driven simulation interface in C++. These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL (tag vhdl) and Verilog (tag verilog), but is more aptly described as a system-level modelling language.
SystemC is standardized as IEEE 1666-2011 (available as a free download). SystemC-AMS is standardized as IEEE 1666-2011.1 (also available as a free download).
Example
#include "systemc.h"
SC_MODULE(adder) // module (class) declaration
{
sc_in<int> a, b; // ports
sc_out<int> sum;
void do_add() // process
{
sum.write(a.read() + b.read()); //or just sum = a + b
}
SC_CTOR(adder) // constructor
{
SC_METHOD(do_add); // register do_add to kernel
sensitive << a << b; // sensitivity list of do_add
}
};
Tag usage
The tag systemc can be used for programming related problems in system level modelling and other related fields. Please avoid theoretical and "refer-a-book"-type questions on stackoverflow.
