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Questions tagged [specman]

Specman is a simulator for `e` (IEEE 1647), an Aspect Oriented Programming (AOP) hardware verification language that enables constrained-random stimulus generation and coverage.

Specman is and EDA tool from Cadence Design Systems that provides an environment for working with, compiling, and debugging testbench environments written in the e language. See also

http://www.cadence.com/products/fv/enterprise_specman_elite

261 questions
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Implementing System verilog’s $value$plusargs() system function in Specman E

What is the equivalent syntax or implementation for System verilog‘s $value$plusargs option in Specman E ? I am working in converting a source code from System verilog to Specman E, I am stuck with implementing $value$plusargs() system function in…
Sreejin TJ
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VIM syntax file for specman

Where can I find an updated syntax file for specman? There are a number of these on the web, but I want one with recommendations.
Nathan Fellman
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Is there "parallel all of" in Specman?

Let’s assume I have this unit unit agent { init_all_regs() @clock is {…}; }; I have a list of agents, the number of agents vary. I want to call the method init_all_regs() all of the agents, so that all of them run in parallel. Is there some…
user3612132
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how can I count the number of set bits in a uint in specman?

I want to count the number of set bits in a uint in Specman: var x: uint; gen x; var x_set_bits: uint; x_set_bits = ?; What's the best way to do this?
Nathan Fellman
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Difference between declaring an event that is sensitive to a simple_port value and event_port

I want to know if there is any difference between the two: 1) simple_port data_valid : simple_port of bit is instance; keep data_valid.hdl_path() == "data_valid_o"; event data_valid_f is fall(data_valid$) @sim; on data_valid_f { -- do some…
renvill
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Specman UVM Scoreboard basic questions

I've built the next (working correctly) Scoreboard/Monitor environment: // Scoreboard : like uvm_scoreboard scbd_port packet_add : add packet_s; scbd_port packet_match : match packet_s; My ADD flow: // Monitor: expected_packet_o : out…
Halona
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Specman on-the-fly generation for multiple constrained items

I have this multiple fields that need to be constrained in this manner: struct my_struct { a : uint; b : uint; c : uint; d : uint; keep 3*a + 4*b + 5*c + 6*d == 206 and a + b + c + d == 50; my_method() @clk_event is { …
renvill
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execute perl from specman

I need to call a Perl script from an E test that I wrote. I need to create an ini file-invoke C script that will create a config file which I need for the test I'm writing. I want the test to invoke the Perl which will handle the ini->C->config…
Chaggster
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Specman coverage: How to cover only that some transition occurred?

I need to make sure that at least 1 change occurred in a specific uint item X, i.e. X had 2 different values (it is unknown what specific values). Something like this: cover some_event { item X : uint = some_uint using no_collect; transition…
Halona
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specman e free tool for learning purpose

I am learning specman e for design verification, I have read some tutorials and learned some code, but i could not find a free tool to try some codes that I learn. so, my question is there any free tool like DVT eclipse that I can use it to learn…
t.tah
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Specman: Why test has not finished after the MAIN sequence is finished?

a test I've wrote does not finishes after the MAIN sequence is finished. I did not raise TEST_DONE objection.. and the objections I did raised were all dropped. Actually the test finished long after all sequence's flow is done, on TEST BENCH…
Halona
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Specman: What is the difference between "define" and "#define"?

What is the difference between define with and without hash mark? Thank you for your help
Halona
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'type' constraint between two different determinant fields

I've read up on the topic of 'type' constraints in e. I saw that it's possible to constrain the types of struct fields, like in this example: extend DATA packet { keep type header is a COP header; }; This means that whenever I'm dealing with a…
Tudor Timi
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Specman macros: How to use optional tags?

I have a macro for defining ports: -- Create simple port define "p_def " as { : inout simple_port of is instance; keep bind(,empty); }; I would like to extend…
Halona
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Dependency Injection before generation

This is a follow up question from my previous question (Difference between "new" and "gen"). Is there a way to pass dependencies into a struct before generation occurs? I'm interested in trying to write my code in a way which is easily tested.…
qzcx
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