sll stands for "shift left logical", an operation on a bit vector in VHDL. Use this tag for questions about this operation in the context of VHDL programming
Performs a logical (filled with zeros on the right) shift left of a vector in VHDL.
Use Model:
signal a_reg : std_logic_vector(31 downto 0);
a_reg <= "10101010101010101010101010101010";
a_reg <= a_reg sll 3;
This will shift a_reg left by three and the new value will be:
01010101010101010101010101010000
