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Questions tagged [qsys]

Qsys is a system integration tool included as part of the Altera Quartus® II software.

Qsys is a system integration tool included as part of the Altera Quartus® II software. Qsys captures system-level hardware designs at a high level of abstraction and automates the task of defining and integrating customized HDL components, which may include IP cores, verification IP, and other design modules. Qsys facilitates design reuse by packaging and making available your custom components and systems, and integrates your custom components with Altera® and third-party developer components.

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I want to implement a circuit in my DE1-SOC based on the SDRAM, where should I start? (I already finished a part)

I want to make a simple project on which I load 10 numbers in SDRAM of my Altera DE1-SOC ready to be taken as input for a Logic Unit I am creating, the logic unit only does a simple arithmetic " Y =(X+1)*(X-1), X is the input and Y is the output…
sujeto1
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How do I generates SPI core in Qsys?

I having some issues with generating SPI master core in qsys. I opened a clean design (with no core in it), and added the SPI core to it and exported all of its signals. When I tries to generate the design, its gives an error about a missing file -…
shortz
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fork join algorithm on fpga

I want to transfer a fork-join problem in fpga. Fork-join in the sense that there will be many small components (> 100) accessing a memory component, processing input data (a few 32-bit vectors) for small amount of cycles (~50) without interactions…
user2609910
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quarts II - Qsys PLL error in modsim

Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL. Investigating a bit further I tried to load just the PLL in modsim and I get…
hoboBob
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Verilog Ports in Generate Loop

For reasons which cannot be avoided (requirements of Qsys), I have several Verilog modules which end up with many ports which would be far easier to work with if they were packed. To try and explain what I mean, here is an example: module foo #( …
Tom Carpenter
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Multiple Interrupt Senders in one peripheral in Qsys

Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated…
Mishka
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Use dma transfert with Cyclone V Avalon-MM for PCIe

Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip-core named «Cyclone V Avalon-MM DMA for PCIe» to do dma transfert. But this ip-core does not support…
FabienM
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Edit top verilog component generated by Qsys

Is it possible to modify Verilog generated by Qsys before Quartus synthesis ? I designed a component under Qsys. I added the design.qsys file under my Quartus (14.0) project and selected it as «top-level». Qsys generate a verilog top component named…
FabienM
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Can't compile my system in Qsys

When trying to assemble the system according to the instructions in this document http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf I get this error message: Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected…
Niklas Rosencrantz
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How to Simulate PCIe Design Using BFMs? Intel PCIe_DDR Design

I am trying to simulate the reference design (PCIe_DDR4) on Terasic DE5a-Net DDR4 edition board. I want to simulate this and confirm meaningful DDR4 read/writes in ModelSim. Referring to Intel Documentation :…
baggins6000
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How to setup the control interface for the Avalon-MM?

In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported. Now I struggle to setup the control interface to access the ADC channels. Mainly…
Norick
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Altera UART IP Core

I am trying to make some tests with an FPGA and while trying to add an UART to my design using the Quartus II v13.0 SP1 and the Megawizard plug-in I realised that there is no UART available there but it is available from Qsys tool. My question is…
osuarez
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