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Questions tagged [pci]

Questions in this tag are only for questions related to the PCI Local Bus standard which is a computer bus for attaching hardware devices in a computer.

Questions in this tag are only for questions related to the PCI Local Bus standard which is a computer bus for attaching hardware devices in a computer.

483 questions
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difference between core.c and pci.c in Linux nvme driver

I want to learn how nvme driver works in Linux, So I look into nvme driver source code here what confuses me is that there are two source file containing "module_init()" core.c module_init(nvme_core_init); and pci.c module_init(nvme_init); I know…
user3094631
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Interfacing with QEMU edu device via Userspace I/O (UIO) Linux driver

I'm looking at QEMU's edu device (source) which provides a basic "educational" PCI device within QEMU, that can be accessed as a PCI device from within a QEMU guest like Linux. I have been trying to get this to work with the UIO driver (Userspace…
davidA
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What is the equivalent of 'Cache line size' in PCIE?

In PCI configuration space, Cache line size indicates system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used…
BasavarajaMS
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PCI nodes in Device Tree

Is it necessary that the nodes shown in "lspci" output, have to be defined in device tree ? I have device tree file for P2041RDB. In that only one node is created for pci i.e. bus 0. Now I have customized the reference board and connected one…
Savan
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How to read a byte of the Serial Presence Detect (SPD) data from the DIMM after 255(FF) bytes?

I have got SMBus Base Address Register, and program the SMBus Transmit Slave Address Register with the DIMM SMBus address, SMBBASE 04h. Then program the SMBus Host Command Register with the DIMM’s SPD data offset to be read, SMBBASE 03h. But the…
powertool
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Reading USB device Vendor ID and Device ID from PCI config space (EFI)

I want to get Vendor ID and Device ID for plugged USB device via EFI program. I can read whole PCI config space I find USB host controller to which My USB device is pugged I can also read whole memory addressed for this controller but I don't know…
elklepo
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Can we use SSE intrinsics to write to a memory mapped PCI device memory

I have a use case where the x86 CPU has to write 64 bytes of data to PCIe slave device whose memory has been mmapp'ed into the user space. As of now, i use memcpy to do that, but it turns out that it is very slow. Can we use the Intel SSE intrinsics…
Anil Abraham
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Linux: request_mem_region returns unusable range

I'm currently working on porting a kernel module for a VME bridge from 2.6 to 3.16. The device is capable of mapping a VME address space to PCI, where the address range that is mapped into can be set by the driver. So the kernel module first tries…
Karsten Koop
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Accessing PCI Device from user space programs

I have a device which would be interface with my processor through pcie. I have written driver for it using the existing pci file operations. Now my problem is how do I access it from user space programs? PCI File operations do not have IOCTL…
vaibhav3002
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Can a Linux device driver wait for a DMA to terminate in the device_remove() function?

I've written a Linux device driver for a PCI device. This device performs DMA operations. An issue arise when the program crashes when a DMA operation is running. Indeed, when crashing, the device_remove() function is called by the system (as if…
Didier Trosset
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PCI Address Spaces

I have a question about the PCI. The PCI has three address spaces; PCI I/O, PCI Memory and PCI Configuration space. Where are they each physically located? In the PCI controller? Or in the devices? Is any of them part of the system RAM?
Isaac D. Cohen
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How does base address register gets address?

I've finished developing a pcie driver for an FPGA under a linux distributiuon. Everything works fine. But I'm wondering where the base address register in the PCI Endpoint of the FPGA gets the base address. When I've generated the PCIe Endpoint I…
user3619609
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PCI BAR memory addresses

Quick question, I was reading the OSDev Wiki page regarding PCI and it says the following - "Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for port addresses. Typically, memory address BARs need…
RJSmith92
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How to force kernel to re-read/re-initialize PCI device IDs?

My machine (running Linux kernel 3.2.38) on boot has wrong subsystem IDs (sub-device and sub-vendor IDs) of a PCI device. If I then physically unplug and re-plug the PCI device while the system is still up (i.e., hot-plug), it gets the correct…
Jahanzeb Farooq
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PCI IDE/(P)ATA differences

I've read some articles about PCI and IDE/ATA, and I'm a bit confused now. The PCI class 0x01 (mass storage controllers) contains an IDE (0x01) and an ATA (0x05) subclass. However, from…
David Szalai
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