Questions tagged [iommu]

IOMMU is a memory management unit that connects a direct memory access-capable I/O bus to the main memory.

Description

In computing, an input/output memory management unit (IOMMU) is a memory management unit (MMU) that connects a direct memory access-capable (DMA-capable) I/O bus to the main memory. Like a traditional MMU, which translates CPU-visible virtual addresses to physical addresses, the IOMMU maps device-visible virtual addresses (also called device addresses or I/O addresses in this context) to physical addresses. Some units also provide memory protection from faulty devices.

An example IOMMU is the graphics address remapping table (GART) used by AGP and PCI Express graphics cards.

I/O virtualization is not performed by the CPU, but instead by the chipset.

Link

IOMMU Wiki

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How to add VFIO-IOMMU in KVM virtual machine (Aarch64)?

I am using aarch64 Linux to test VFIO-IOMMU feature in KVM VM. The host is cortex-A78 running Linux-5.10.104 (with VFIO_IOMMU enabled). The guest OS is Ubuntu-22.04 (Linux-5.15, also with VFIO_IOMMU enabled). The VM is created with virt-manager…
wangt13
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Reading 0 when reading SMMUv2 registers from user space in Linux

There is an ARM SMMUv2 in system, and I want to read its memory mapped registers from Linux user space. So I opened and mmap /dev/mem, the offset is the physical address of SMMU_BASE got from DTS, e.g. 0x8000000. But when I read from the mmaped…
wangt13
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What are transactions and streamID in ARM SMMU

I have basic query regarding ARM SMMU, as per following link: https://www.intel.com/content/www/us/en/docs/programmable/683567/21-3/stream-id-falconmesa-stratix-10.html "Each transaction is also classified by a 10-bit stream ID. The stream ID…
Milan
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How to configure IOMMU protection for my hypervisor?

I'm developing my own bare-metal hypervisor over intel vt-x technology. My goal is to make it inaccessible to the OS I'm running over my hypervisor in any way, therefore I configured an EPT table to protect from memory access. I believe that now I'm…
matank001
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PCIe DMA aarch64 0x10 Translation Fault

I'm trying to write a PCIe driver to DMA pages from the host memory to an FPGA. My host setup is Cavium ThunderX2 and my FPGAs are Xilinx Alveo U50. A DMA from/to the host causes the ARM SMMU v3.4 to throw an event 0x10 Translation fault. I'm using…
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with IOMMU, why don't we have to pin the DMA buffer pages?

I heard from somewhere, without IOMMU, the S/W should pin the DMA buffer until the DMA is complete because the physical page can be assigned to another processor in the mean time. And I heard that if we have IOMMU for the device, we don't need to…
Chan Kim
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kernelstub can't find kernel or initrd image on Ubuntu 21.04

I'm trying to enable Intel_IOMMU with the --add-option flag for kernelstub, but the command always fails, returning that kernelstub cannot find the kernel image. I tried to manually set the kernel path, but it then returns that it cannot find the…
KCGD
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Can I call dma_map_single() on DeviceB using an addresses returned from dma_alloc_coherent on DeviceA?

I am writing custom linux driver that needs to DMA memory around between multiple PCIE devices. I have the following situation: I'm using dma_alloc_coherent to allocate memory for DeviceA I then use DeviceA to fill the memory buffer. Everything…
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Why does my host OS experience high system cpu usage on cores performing networking when using SR-IOV?

I am trying to determine why my KVM host shows high system CPU usage for a specific guest. I have setup a KVM host (Ubuntu 20.04) to host a guest VM (Ubuntu 20.04). I configured the guest to use cores (via vcpu / vcpupin / emulatorpin) from the…
Nick
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VFIO - igpu passthrough on Intel 4770 to a virtual machine (Host Os Proxmox)

I am running the latest Proxmox (6.3-3 at this time, fully updated) and attempting to passthrough the onboard GPU on my Core i7 4770 CPU to a Windows 10 VM. I have already enabled iommu on the system and also told grub to not let the system claim…
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Linux DMA 32-bit dma_alloc_coherent wrong behavior when intel_iommu=on

I'm writing a linux device driver to DMA data from FPGA into CPU RAM via PCI express. Running 64 bit Centos 8.1, kernel 4.18.0-147.3.1 on Intel Platform. The implementation follows the DMA-API-HOWTO. The DMA is 32-bit and the driver uses consistent…
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How IOMMU unmaps the IOVA comming from different pheripherals through DMA

I have been trying to get the information on this for so long and still haven't got anything solid. So, what I have learned so far is that the IOMMU converts the IOVA provided by the DMA to the physical address and reads or writes from/to the…
Jigar Agrawal
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Is an address in a PCI transaction translated by IOMMU by default on x86 platform?

I know that PCI has feature called ATS to translate virtual address to physical address, but I am not sure whether it is enabled by default in current x86 platform. If it is, how should I generate virtual address and corresponding page table in…
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