Stack Overflow
Stack Overflow

Questions tagged [instructions]

Questions about instructions of real CPUs, VMs or compiler IRs.

Questions about instructions of real CPUs such as ARM and x86, virtual machines such as Java, or compiler internal representations such as LLVM.

574 questions
0
votes
0 answers

What causes the retired instructions to increase?

I have a 496*O(N^3) loop. I am performing a blocking optimization technique where I'm operating 2 images at a time instead of 1. In raw terms, I am unrolling the outer loop. (The non-unrolled version of the code is as shown below: ) b.t.w I'm using…
quantumshiv
  • 97
  • 10
0
votes
2 answers

DrJava - an "Auto Import Claas" error

I'm a beginner at Java, when this was added; it gave me ab error, all in this picture! I Compiled then to Interactions
Sa77a
  • 93
  • 1
  • 5
0
votes
2 answers

CPU instruction reordering

Our processors are allowed to reorder the instruction in order to gain some performance benefits, but this may cause some strange behaviour. I'm trying to reproduce one of this issues on the base of this article. This is my code: int a,b; int…
fjanisze
  • 1,234
  • 11
  • 21
0
votes
1 answer

Use ReadProcessMemory to record pointed instructions

I'm trying to log pointed instructions with ReadProcessMemory, in fact I use EIP register to get the next insctruction address. Next, I use distorm lib to display mnemonic. But ReadProcessMemory reads nothing. void display_instruction(Debuggee*…
nasm
  • 15
  • 4
0
votes
2 answers

NASM - Using several BITS directives in one file

I am writing a second stage bootloader, a part of whose responsibility will be to enter 32 bit protected mode from 16 bit real mode. My code has some initializing real mode code, a few real mode functions, protected mode code and a few protected…
Cygnus
  • 3,222
  • 9
  • 35
  • 65
0
votes
1 answer

How do I compare ASM instruction speeds?

I know that xorq %rax,%rax is faster than movq $0,%rax because my compiler has told me. However, if I didn't know the answer, what should I do to compare xorq and movq performances? What I have tried is this: int main(void) { long a; long i =…
user16538
  • 1,080
  • 1
  • 8
  • 17
0
votes
1 answer

Count the number of instruction cycles of each instruction in the assembly generated for ARM

How can i count the number of instruction cycles for each instruction in the assembly generated for a C/C++ program for ARM? Is there any tool for it? I don't want to look into ARM instruction set each time.
sarda
  • 213
  • 2
  • 7
0
votes
3 answers

Loading from memory whose size is larger than the available size in an instruction

Processors these days are mostly 32 or 64 bit. This means that the instructions they process have this size. We often hear that a 32-bit operating system is limited to 4GB=(2^32 bits) of RAM due to the fact that the length of a RAM address needs to…
BrainOverfl0w
  • 257
  • 1
  • 3
  • 13
0
votes
1 answer

alignment requirement for powerpc icbi and dcbf cache instructions

I have inherited some PowerPC 750FX code. A handful of functions flush the instruction and data cache with icbi 0,3 # instruction cache block invalidate and dcbf 0,3 # data cache block flush respectively. The code makes sure the Register 3…
Jens
  • 69,818
  • 15
  • 125
  • 179
0
votes
2 answers

Verilog branch instruction MIPS

I am trying to understand how the verilog branch statement works in an immediate instruction format for the MIPS processor. I am having trouble understanding what the following Verilog code does: IR is the instruction so IR[31:26] would give the…
CodeKingPlusPlus
  • 15,383
  • 51
  • 135
  • 216
0
votes
2 answers

Having trouble understanding memory addressing in assembly

I'm looking at a piece of assembly code and I'm stuck trying to make sense of something: incl (%ebx, %eax, 4) What exactly does this do? I tried plugging it into a .s file and compiling then watching registers in GDB but when it passes the…
Riptyde4
  • 5,134
  • 8
  • 30
  • 57
0
votes
2 answers

Explaination of assembly code

These are the 4 lines of assembly code. i am trying to understand them. (It is intel syntex.) – mov eax, ebx – mov eax, [ebx] – mov eax, [ebx+ecx*X] (X=1, 2, 4, 8) – mov eax, [ebx+ecx*X+Y] (Y= one byte, 0-255 or 4 bytes,…
narayanpatra
  • 5,627
  • 13
  • 51
  • 60
0
votes
1 answer

Profiling CUDA code: Unexpected instruction counts on coalesced memory reads

I am profiling a very dump sorting algorithm for small input data (= 512 elements). I am invoking a kernel that reads coalesced form an array of structs. The struct looks like this: struct __align__(8) Elements { float weight; int…
Michael Haidl
  • 5,384
  • 25
  • 43
0
votes
1 answer

Machine code generation, memory access / register operation patterns and performance?

I had a really hard time formulating a title for this question, and I don't think I did very well, so if anyone has a better idea, the edit button is yours. Considering that memory operations cost 3-4 cycles in the absolutely best scenario and…
user2341104
0
votes
1 answer

How to insert more than one call instruction using CreateCall in LLVM

I am running a module pass on my source code using llvm. For a certain instruction, I want to insert 2 or 3 instructions before the next instruction in the code. What I am currently doing is passing Instruction->getNextNode() as the last argument…
Mahwish
  • 101
  • 2
  • 9
1 2 3
…
38 39