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Questions tagged [gnu-make]

This tag is for questions about `gmake`, the GNU version of the `make` utility to maintain and update programs.

GNU Make is the GNU implementation of the Make utility. It is probably the most common version in use today.

GNU Make supports extensions to the Make language beyond the POSIX standard, therefore GNU Make solutions may not work under other versions, so the gnu-make tag is appropriate for questions from those using GNU Make, or pertaining to makefiles written for it.

Documentation

The latest GNU Make manual can be found in several formats here.

See also

make makefile

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How can I highlight the warning and error lines in the make output?

Sometimes, make's output fills the screen. It's a little bit hard to identify all the warning and error message lines. I know may shell color output can help Can anyone can help me?
Eric guan
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How to write a Makefile with separate source and header directories?

Following this tutorial... I have 2 source files and 1 header file. I want to have them in separate directories like in the tutorial. So I set this project up: . ├── include │   └── hellomake.h ├── Makefile └── src ├── hellofunc.c └──…
iBeyondPower
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3 answers

GNU Make pattern to build output in different directory than src

I'm trying to create a Makefile which places my .o files in a different directory than my source files. I'm trying to use a pattern rule so I don't have to create identical rules for each source & object file. My project structure looks something…
mrb
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3 answers

GNU make cheat-sheet

I'm learning to work with GNU make and I'm reading the manual (which is very good) but I'm missing a cheat-sheet for quick reference. Is there any good? Note: It's quite hard to find to google this.
MartyIX
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Makefile: Filter out strings containing a character

I'm trying to filter out strings that contain a particular character, but it doesn't work. I guess make does not support multiple % patterns? .PHONY: test test: echo $(filter-out %g%, seven eight nine ten) Gives: $ make test echo seven eight…
Steve
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4 answers

gnu make "Removing intermediate files"

I have the following rules define compile_c $(ECHO) "CC $<" $(Q)$(CC) $(CFLAGS) -c -MD -o $@ $< @# The following fixes the dependency file. @# See http://make.paulandlesley.org/autodep.html for details. @# Regex adjusted from the above to play…
Bob
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Convert Cygwin path to Windows path in a makefile

How can I convert a Cygwin style path ( /cygdrive/c/foo/bar ) to Windows style ( C:/foo/bar ) (yes, with / going forward) in a GNU makefile? I have the situation of using Cygwin's make with a GCC that does not understand Cygwin style paths, so paths…
grrussel
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1 answer

Function "patsubst" in Makefile

From the docs: $(patsubst PATTERN,REPLACEMENT,TEXT) Finds whitespace-separated words in TEXT that match PATTERN and replaces them with REPLACEMENT. Here PATTERN may contain a % which acts as a wildcard, matching any number…
Ji Cha
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3 answers

Depend on the make file itself

In the event that a Makefile itself is changed, a safe bet would be to consider all targets out of date. Is there a clever way to add this dependency? Are there any alternatives?
Matt Joiner
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1 answer

Force gnu make to rebuild objects affected by compiler definition

I have a makefile that takes options at the command line make OPTION_1=1 Based on the value it will add additional compiler definitions to a subset of objects. ifeq ($(OPTION_1), 1) CC_FLAGS += -DOPTION_1_ON endif The change in the definition…
Oliver
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What is the difference between "make" and "make all"?

I have a Makefile with the following structure (working example). .PHONY: image flashcard put-files put-files: @echo "=== put-files" image: @echo "=== image" flashcard: @echo "=== flashcard" all: put-files image flashcard @echo…
Dave Vogt
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4 answers

multi-wildcard pattern rules of GNU Make

I want to write something like regex: SRC:="a.dat.1 a.dat.2" $(SRC): %.dat.%: (\\1).rlt.(\\2) dat2rlt $^ $@ so that a.dat.1 and a.dat.2 will give a.rlt.1 and a.rlt.2. In GNU Make info page, it says "the % can be used only once". Is…
heroxbd
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How to trace Makefile targets for troubleshooting?

We have a long and complicated Makefile in our build system. Is there a good way to trace exactly which targets get executed for a given make invocation?
zer0stimulus
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3 answers

GNU make: Extracting argument to -j within Makefile

I've been searching for an hour, and this information appears to be nowhere... I'd like to be able to extract (and possibly use) the number of requested make "jobs," as passed via the -j option, or by Make itself in the case of sub-makes, in the…
JW Peterson
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27
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3 answers

making all rules depend on the Makefile itself

When I change a Makefile, its rules may have changed, so they should be reevaluated, but make doesn't seem to think so. Is there any way to say, in a Makefile, that all of its targets, no matter which, depend on the Makefile itself? (Regardless of…
reinierpost
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