Questions tagged [e]

e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification testbenches.

e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification test-benches.

http://en.wikipedia.org/wiki/E_(verification_language)

The e language uses an Aspect-Oriented Programming (AOP) approach, which is an extension of the object-oriented programming approach to specifically address the needs required in functional verification.

AOP is a key feature in that it allows for users to easily bolt on additional functionality to existing code in a non-invasive manner. This permits easy reuse and code maintenance which is a huge benefit in the hardware world, where designs are continually being tweaked to meet market demands throughout the project life-cycle.

AOP also addresses cross cutting concerns (features that cut across various sections of the code) easily by allowing users to extend either specific or all instances of a particular struct to add functionality. Users can extend several structs to add functionality related to a particular feature and bundle the extensions into a single file if desired, providing for more organized file partitioning.

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Specman: Why DAC macro interprets the type as 'string'?

I'm trying to write a DAC macro that gets as input the name of list of bits and its size, and the name of integer variable. Every element in the list should be constrained to be equal to every bit in the variable (both of the same length), i.e. (for…
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Specman e: Is there a way to constrain the amount of set bits in a number?

I have unit field events: events:uint; The values of events not so interesting as the amount of set bits in it. I would like to constrain the ranges of the amount of set bits in the events. Is there a way to do it? Thank you for your help.
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Specman e: How to disable coverage of an instances / units?

In my verification environment under sys there is an instance of timer_sve. Under timer_sve I have 2 other instances: timer and ocp_master: extend sys { timer_sve : timer_sve_u is instance; }; unit timer_sve_u { timer : timer_u is…
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Specman e: How to constrain distribution of values inside list of list?

I have my_list (list of structs) that defined this way: struct my_struct { comparator[2] : list of int; something_else[2] : list of uint; }; my_list[10] : list of my_struct; I need to constrain distribution of values of comparator[0] and…
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Specman e: When colon equal sign ":=" should be used?

I saw in some Specman e code example the use of := (colon-equal sign), e.g.: var regs_type := rf_manager.get_exact_subtype_of_instance(graphics_regs); When and why should we use := ? Thank you for your help.
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Specman coverage: Is there a way to define ranges using variable?

I have comp_value that gets values between 1 .. 100. In addition I have an input variable period (of the same range). I need to cover 2 ranges of comp_values: [1..period] and [period+1 .. 100]. Something like this: cover some_event_e is { …
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Specman DAC macro: How to define 2 inputs of different type (uint and string)?

in my verification environment I have different registers' types with almost the same name that differs only by index, e.g.: timer_load_0, timer_load_1 etc.. I try to create a macro that gets 2 parameters: string (the 'name' of the register without…
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Specman: Is there a way to access different variables by some index?

in my verification environment I have 3 different registers with the same fields: load_0, load_1 and load_2. Now I have the same function duplicated 3 times for every register and differs only in one line: duplicated_func_0() { value =…
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Specman e compilation error: No such variable 'XXX'

I define a variable my_reg_file in function post_access() (this function is a vr_ad hook for implementing side effects): //file1.e extend TIMER_LOAD_0 vr_ad_reg { post_access(direction : vr_ad_rw_t) is first { var my_reg_file : TIMER…
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Specman UVM: How update a value of a register when the value was written to another register?

(in my verification environment we use vr_ad package.). I try to implement the next: When data is written to one of the registers (timer_load), another register (timer_bgload) should be updated with the same data. I've found the next example in UVM…
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Specman UVM: What is the difference between write_reg { .field == 2;}; and write_reg_fields?

I'm working with vr_ad package for e. My question is: What is the difference between 2 following macros for modifying registers (suppose foo register consists of 2 fields: field1 and field2): 1) write_reg foo {.field1 == 1;}; 2) write_reg_fields…
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Looking for Specman methods to get first/next/last enumerated value

Are there built-in methods in Specman that give me the value of the first, last, and next value of an enumerated variable? For example: type color_e: [blue, green, red, yellow, orange];` var color: color_e; color =
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Why is the following statement not allowed in e

In an e file, it's perfectly legal to say: print 5; But at the same time, the following thing doesn't work: type some_type_e : [ VAL1, VAL2 ]; print VAL2; // issues a compile error The parser expects VAL2 to be a variable name and doesn't…
Tudor Timi
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Static fields/methods in e

Is there any technical reason I am missing for which e doesn't have static fields/methods? I've looked up the LRM and there is no mention of anything like this. There are workaround (like this one:…
Tudor Timi
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Is it allowed to have two structs with the same name?

I have the following code in some e file: <' package my_package; struct packet { foo() is { print "Hello"; }; }; '> And my top file imports several files, including this one, and at some point it calls the foo() method. Now, by…