Questions tagged [digital-design]
79 questions
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Verilog calculator with 16 bit inputs
Hey guys I'm stuck on a project and am looking for some insight. The problem is:
Build a Verilog module named “calculator” that takes in two signed 16-bit numbers named “in1” and “in2” and performs the following functions depending on the value of a…
python paradise
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Compilation error: A net is not a legal lvalue in this context
I am a newbie to Verilog and had a problem while defining a if-else loop. The error message is
A net is not a legal lvalue in this context" for all assign statements in the given code.
always @(adbar)
if (adbar==1'b1)
begin
assign…
Envyh121
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1 answer
Encoder and My Challenges on Digital Logic
in following Encoder, the priority of bigger number is bigger. if the initial state is 0, after how many clock pulse, Q after being 1, change states to zero.
My professor, say (3), why ?
user4559497
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2 answers
Design does not fit ispLEVER
Hi I am trying to create a .jed file from a vhdl file through ispLEVER the problem appears when I try to create the fuse map and a port of 1 bit named le can´t be assigned to pin 23 (The GAL22V10-15LP has 24 pins)
Here is my vhdl code
library…
Helbert Gonzales
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1 answer
using demorgan law to change function to inv-nand
we have :
F = A C'D' + B'C'
Use De’Morgan’s law to convert the NOT-AND-OR function to NOT-NAND
function (with minimum number of gates). Show the conversion steps. Keep in
mind that you have only NAND gates with fan-in = 2.
i did this but i…
Omran
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Programmable Logic Devices
I have a confusion in understanding the structure of PAL device.
My first question is that if we buy a PAL device , then how can we know that how many min terms are added by each OR gate in the OR array? In other words I am asking, is there any…
Zia ur Rahman
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Wires are not connected in the RTL
I have some strange problem, some wires are not connected in my design.
I am trying to make a simple register file (I am using Xilinx ISE). This register file contains 32 registers, each is 32-bit size. The register file has two MUXs for reading…
user586399
-1
votes
1 answer
Verilog code is compiled but there is no "vcdplus.vpd" waveform file being created when using "$vcdpluson" - FSM Sequence Dectector
My verilog code for my Finite State Machine - Moore (Non-Overlapping) - Sequence detector is not generating a "vcdplus.vpd" waveform file after I have compiled. I'm compiling my verilog code with vcs -debug-access+all . After that I run…
harhote
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1 answer
Programmable Logic Array (PLA) Design
I need to design Programmable Logic Array (PLA) circuit with given functions. How can I design circuit with POS form functions. Can someone explain that? enter image description here
hakan-eryaz
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1 answer
Where to place the SystemVerilog interfaces, and how to name the interfaces and the files
I am writing some interfaces for my design in SystemVerilog, I have many of them. I was wondering if there are some specific guidelines regarding how to organize them.
right now I have all of my interfaces in one file. I was wondering if I should…
flora
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1 answer
How do I drive a signal from 2 sources in system verilog
I'm trying to write a RTL model in which I monitor independent clock sources. These clock sources can have variable frequency (range 5 to 50MHz)
Let us say clk1 and clk2. I'm trying to drive a signal 'toggle' which is set '1' at every posedge of…
user3547407
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1 answer
Verilog Increment Decrement counter using Altera Board
Hey so I'm basically brand new to Verilog and not quite sure how the syntax works and things like this.
The assignment is as below
Use a push button and a switch on the Altera board to increment or decrement a 4 bit counter. The value of the…
Lucas Wetherall
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1 answer
wrong values at adder output in verilog module
I have written a gate level code for adder in Verilog. The output the adder is shown below. As you can see the sum and cout are always in z. I don't know why. Could you check what am I missing ? Thanks for your time.
OUTPUT:
a = x, b = x, cin = x,…
user_rak
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3 answers
Denormalization IEEE
I'm working on a Digital Design project (Verilog) involving IEEE double precision floating point standard.
I have a query regarding IEEE floating number representation. In IEEE floating point representation, the numbers are represented in normalized…
Displayname
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1 answer
Verilog Testbench Implementation
I'm trying to implement a verilog program and the majority of the test cases are passing (1,188 out of 1440). My question however is that my expected overflow output is currently being displayed at 0 while the expected value is supposed to be 1.…
mur7ay
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