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Questions tagged [digital-design]

79 questions
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VHDL Counter returning 'X', unknown value

I am trying to create a 4 bit counter with instantiated components, shown below. When I simulate, the output toggles between 0 and X(an unknown signal). I'm not sure what is wrong. simulations, circuit diagram and code are shown below. 4 Bit modulo…
Chris
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Synchronous vs Asynchronous logic - SR-Flipflop

I have came across a logical design where I have some questions. The first questions is whether there are two separate SR flip-flops in this design? The second question is whether a clock normally is used to propagate the inputs through the design…
user2466860
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Store a bitvector in flipflops instead of memory - Chisel

I would like to know the difference in usage of Reg and Mem in Chisel, and how I can decide which of these to choose in common scenarios. I would assume that Mem is the best idea when storing large amount of data, because it would store the data to…
Mrchacha
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How to perform fixed point representation in vhdl without introducing any package

I have a 32bit fractional number with 4 integer bits and 28 fractional bits and I am interested in implementing it in VHDL without the use of package such as ieee_proposed.fixed_pkg.all . Is there any other method of representing this 32 bit number…
Vijay Karthik
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NGSpice Monte Marlo analysis, how to pass the parameters to the sub-circuit?

Question: How to pass the modified device model parameters (such as W, L, Tox) to the sub-circuit during Monte Carlo iterations loop? Tool version: [boris@E7440 inverter]$ ngspice -v ngspice compiled from ngspice revision 23 Written originally by…
Boris L.
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Flip-flop and latch inferring dilemma

Could someone explain to me why a latch would be inferred instead of a flip-flop? always_ff @ (posedge clk, negedge rst) begin if (!rst) a <= '0; end Shouldn't the fact that the always block is sensitive to a signal edge be enough to infer a…
evilpascal
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Static Hazard 1 and One Circuit Problems?

I read about Static Hazard. We know Static 1-hazard is: Input change causes output to go from 1 to 0 to 1. My note covers a Circuit as follows: My notes says: When B=C=D=1, for any changes in A values, it's probable to have Static Hazard 1. But I…
user5912880
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VHDL clock divider flips between 0 and X every clk cycle

I'm starting out trying to learn VHDL after doing a little bit of Verilog. This is my attempt at creating a clock divider: (largely taken from Making a clock divider) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity…
bob
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Number of Prime Implicant and EPI

My TA solve this problem, Number of Prime Implicant (PI) for f(a,b,c,d)= Sigma m(0,2,4,5,8,10,11,13,15) is 7 and number of Essential PI (EPI) is 1. how this will be calculated? I think it's wrong. any idea? My solution is :
user4591951
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Karnaugh Map whic one is true?

I have a karnaugh map question. In the Digital Design course teacher learnt but I couldn't understand here clear. We can see in the picture. In the first one, we use all 1s and have 4x3 1s. In the second one we have 8x2 1s and we use some 1s two…
user119949
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Design an OR gate only using Demultiplexers

Show the OR gate operation by only using de-multiplexers. I know it is quite impractical implementation but these types of questions are being asked in placement tests. https://i.stack.imgur.com/mQAZD.png check out OR gate truth table if you want…
srand9
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How to perform base-5 addition , when negative place values are given?

In a base-5 number system having the digits T,M,0,1,2 and their place values are -2,-1,0,+1,+2 respectively, then: What is the maximum decimal value that can be formed? (MT01) + (1TM0) = ?? This question was given in a recruitment test of a VLSI…
srand9
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Function Wash not increasing value in sec signal in VHDL

I'm very new to VHDL and for my digital design project I have to make a simulation of a washing machine in a DE10-Lite FPGA with finite states. Everything seems good so far but when it's turn for the impure function Wash to work, it looks like…
Adolf RJ
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1 bit comaparator using 2x1 mux ? Create First 1 bit magnitude comparator and implement on mux?

I know What is the comparator but i don't know how to implement with Mux Please Give Answer Of Hoe to Design 1 bit comaparator using 2x1 mux, I Create First 1 bit magnitude comparator in this we have two input A and B And we have three output…
Meet Bhatt
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Writing A'B'CD+ABC' using two inverters and 5 2:1 multiplexers

The question says draw F(A,B,C,D)=∑(3,7,11,12,13). I derived A'B'CD+ABC'. I am trying to draw it using two inverters and 5 2:1 multiplexers but i couldn't connect the output to the separate components i wrote. I know the correct answer but i just…
zedyjy
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