Questions tagged [digital-design]
79 questions
1
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1 answer
Why do I get run time fatal error - Range width expression must be positive - for my up counter design?
I am trying to design a 17-bit ripple up counter using a positive edge triggered d flip flop in my design. Here is my code:
`timescale 1us/ 1ns
module upcounter (clk, pr, clr, out);
input wire clk;
input wire pr;
input wire clr;
…
MD. SHAZZAD HOSSAIN
- 11
- 1
1
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1 answer
how to add in binary
I don't understand when 100 appear in add what I should do. what the carry for the next step? They are marked with red and blue colors
Faeze Moosazade
- 23
- 5
1
vote
2 answers
Continuous assignment with 0 delay not getting the expected value after a signal positive edge
I have implemented an 8 bit serial-in parallel-out register in SystemVerilog and I'm trying to test it. I'm using Icarus Verilog as simulator.
In the test bench, I send 8 bits and wait for the rising edge of a signal, then check the obtained…
Dan
- 2,452
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- 45
1
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1 answer
JK-Flip Flop: K-Map to find the Value of Next State (Qn+1)
Given the Truth Table, Characteristic Table and Excitation table for a JK Flip Flop. I am doing a K-Map to find Qn+1 (next state) given J, K and current State. The K-Map from a tutorial explaining this is shown below:
Why isn't JK' (not K) not…
Ash Rivers
- 121
- 4
1
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1 answer
Problem while implementing JK-Flip Flop in VHDL
I'm trying to implement JK flip-flop in VHDL, and here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity jk_flip_flop is
port(
J, K : in std_logic;
clk : in std_logic;
Q, Q_bar : out std_logic
);
end…
theCursedPirate
- 165
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1
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1 answer
Can somebody explain the reasoning behind decimal to binary conversion?
I know the concept of division by 2 & then taking the remainder but I want to know how this method actually works. I want a mathematical derivation for this.
Tarun Gupta
- 25
- 5
1
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1 answer
Connecting Waveshare High-Precision AD/DA Board (ADS1256) to DE10-Nano Kit
I'm currently working on an ECG project and I'm having some difficulties using the Waveshare High-Precision AD/DA Board (which has an ADS1256 ADC and is meant for use with RPI) with the Terasic DE10-Nano Kit.
I'm using an Altera SPI Master…
fin121
- 21
- 3
1
vote
1 answer
D FlipFlop sequence generator for the sequence 1101011 does not generate results
I have created a module for DFlipFlop in DFF module and instantiated 4 of them in seqgen module. I am not able to generate results. Can you please help me where I am going wrong?
module DFF(input d, input rstn, input clk, output reg q);
always…
Kakarot
- 45
- 4
1
vote
2 answers
always block with no sensitivity list - $display not executed
When I run the following Verilog code I get an error:
warning: @* found no sensitivities so it will never trigger.
module main;
reg b;
always @(*) begin
$display("entered always block/n");
end
endmodule
Could someone please…
Ashlesha Sunil Agate
- 43
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1
vote
1 answer
Verilog Constructing synchronous 4-bit counter using negative edged JK Flip Flop testbench problem
I am constructing a 4-bit mod 12 counter
(0->1->2->...->11->0) in Verilog.
However when I try to simulate this code with testbench in Vivado FPGA,
it doesn't seems to operate correctly. Output of the counter module always shows 0.
I tried to modify…
StonerDK
- 11
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- 3
1
vote
1 answer
4-bit synchronous double down counter jk flip flop
Recently, I am trying to learn digital design and Verilog HDL. I am currently working on flip flops. I was trying to construct a 4-bit synchronous double countdown (down counter) with jk flip flop.
Ex: 1111 - 1101 - 1011 - 1001 - .. (15 - 13 - 11 -…
exxe
- 11
- 2
1
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0 answers
How can I attach a shape to a port in graphviz?
In logic design convention, a clock input port is designated by an embedded triangle while an active low port has a bubble as shown in this d-flip-flop example.
Now the bubbled I/O's I can do (if somewhat counter-intuitively) using arrowhead and…
Eric Edwards
- 19
- 2
1
vote
2 answers
Clock domain crossing signals and Jitter requirement
I am reading the DVCON paper 2006 "Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertings" by Mark Litterick. I am confused with some of the statements
Page 2 Section 4.2 Input data values…
Sanjeev Singh
- 141
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1
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1 answer
Ouput of adder module is always don't care [Verilog]
I know VHDL and now I try to do a bit of verilog. I have two files, one that contains a counter and another that contains a 32 bit full adder.
Counter.v:
module counter (
input clk,
input enable,
input reset,
output reg [3:0] count
…
sloeberGJ
- 355
- 3
- 13
1
vote
1 answer
Net, which fans out, cannot be assigned more than one value
I am trying to design an 8-bit multiplier based on 4-bit multiplier. so this is my code:
module _8bit_multiply(a, b, q);
input [7:0] a;
input [7:0] b;
output [15:0] q;
wire [7:0] q0;
wire [7:0] q1;
wire [11:0] q2;
wire [11:0] q3;
wire [7:0]…
J. Koushyar
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