In [computer-architecture], data hazards, control hazards or structural hazards can exist between two nearby instructions. CPU pipelines need to handle them, or require software to avoid them, to correctly execute code.
Questions about hazards should usually also be tagged computer-architecture.
A pipelined CPU starts working on an instruction before completely finishing previous instructions. Maintaining correctness while doing this requires avoiding hazards, for example making sure that an instruction reading a value from a register actually gets the right value, even if it was only written by the previous instruction. (Read After Write (RAW) data hazard).
Data hazards, control hazards, and/or structural hazards can exist between two nearby instructions. CPU pipelines need to handle them, or require software to avoid them, otherwise execution could give wrong or unpredictable results.
See Wikipedia for details:
- https://en.wikipedia.org/wiki/Hazard_(computer_architecture)
- https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Hazards
- https://en.wikipedia.org/wiki/Memory_disambiguation (avoiding / detecting presence or absence of store/reload memory hazards)
- https://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/ high performance implementations of that in modern x86 CPUs.
Things this tag is not about:
- hazard - a term in statistics, for survival analysis.
- Hazard pointers, a software technique in multi-threaded programming.
(Use multithreading and/or lockless)
