DEC Alpha, aka Alpha AXP. The 64-bit RISC CPU architecture with famously weak memory-ordering semantics, and (in early versions) no byte or 16-bit load/store instructions.
DEC's Alpha architecture, originally known as Alpha AXP.
It's a 64-bit RISC ISA with famously weak memory-ordering semantics. It's the only well-known architecture that requires a read memory-barrier instruction to guarantee even dependency ordering (C++11's std::memory_order_consume).
Only some hardware microarchitectures could do this reordering in practice, and even then it was extremely rare, making use of the slow barrier instruction even more annoying.
Alpha was also (in)famous for not providing byte or 16-bit loads/stores in early versions of the architecture, instead providing instructions to shift-and-mask.
These architectural simplifications allowed Alpha to run at high clock speeds while still getting a lot done per clock. It was for some years the fastest hardware available.
- http://alasir.com/articles/alpha_history/press/alpha_intro.html summary ISA design.
