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Questions tagged [addressing-mode]

An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

From Wikipedia (Addressing mode):

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

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base index addressing of array in NASM

This is my nasm code: extern fprintf extern printf extern stdout section .data mas dw 1,1,1,1,1, 2,2,2,2,2, 3,3,3,3,3, 4,4,4,4,4, 5,5,5,5,5, 6,6,6,6,6, 7,7,7,7,7 fmtstr db "%d", 10, 0 section .text global main main: push rbp …
Саша Волотко
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What does "A1114E: Expected register relative expression" mean?

Hi im trying to call a assembler subroutine from c and get this error. On the Arm websites, there is just stated that this error exists.. C Code #include extern void out_word(uint32_t out_address, uint32_t out_value); extern uint32_t…
tom
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An error occurs after replacing a variable value to a new one

When changing the value of a variable an error occurs invalid effective address. mov bl, var mov [bl], 'a' mov al, [bl] <--- here mov ah, 0x0E int 0x10 var db 'H' As I know al is 8-bit and bl is a pointer pointing to 8-bit memory size. There is…
Lion King
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Why does FASM successfully assemble code with 32-bit effective addresses and the directive `use16`?

For example, the following code FASM will assemble successfully. USE16 MOV [ECX+0FEh], BX Assembler's stdout: flat assembler version 1.73.25 (1048576 kilobytes memory) 1 passes, 7 bytes. In my mind, 32-bit addresses are not allowed in 16-bit…
iEPCBM
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Correct addressing mode

For a program I'm writing in assembly %eax points to a memory address which contains a value that I want to move into %rdi. To do this I implemented the following: mov (%eax), %rdi However, this gives a segmentation fault. How come this gives a seg…
user16806508
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Not understanding this instruction format: movq b, a( , b, c)

I have some assembly code that uses movq with the destination operand having the triple-argument parentheses: movq %rax, a(, %rax, 8). From my understanding, a(, %rax, 8) = a + 8 * %rax, but I think it has something to do with a matrix also, (I just…
Satan Lucifer
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difference between ldmia.w sp, {r1, r2} and ldmia.w sp!, {r1, r2}?

I am working in a binary analysis project and I came across two different variants of ldmia arm assembly instruction. ldmia.w sp, {r1, r2} ldmia.w sp!, {r1, r2} I know ldmia.w sp!, {r1, r2} is a synonym to pop {r1,r2}. but what about ldmia.w sp,…
hany erfan
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Intel 8086 assembly - Indirect Addressing and Compare instruction (MASM)

I'm trying to compare a value in the data segment (an item in an array) to the ASCII character value for a space (20h, stored in a register) using a cmp instruction in MASM. The instruction i'm attempting to use is: cmp [ds:bp + si + 1],cx My goal…
CompSciStudent
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Two questions about MIPS instructions

First question: I know that by definition the instruction Beq has at first two registers and then a label where to jump to. However, when I run Mars compiler I get that for example: "beq $s6, 1, Lable" is running well. I would like for explanation…
Chopin
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ARm prfm and prfum instructions

can someone explain what is the difference between the arm instructions prfm and prfum and usage of these…
Thomas
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Question on Aarch64 assembly address formats

I am new to linux GDB, and I have a questions on Aarch64 assembly: On my assembler dump, there are the following lines: 0x0000005555555788 <+36>: str w0, [sp, #24] 0x000000555555578c <+40>: ldr w1, [sp, #24] I know what LDR and STR…
Cyh1368
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Addressing modes involving ESP?

I was studying assembly and I would like some additional clarifications for the below code MOV DWORD PTR SS: [ESP+16], 6E616C41 So basically where is it loading 6E616C41 to? I've learned that stack grows in decreasing order in some architecture so…
Nimrod
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RIP Register at compile time

Does linker or compiler count RIP during compilation? If no, how does that instruction work? There will be hardcoded at linking time address, or it is special feature of processor architecture, that allows pointer arithmetic at runtime? leaq …
Belenot
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How many memory references are required by the CPU to execute immediate address instruction and why?

In immediate addressing mode I know that instead of operand's address we have the value of operand in the instruction itself. So, does CPU requires any memory reference as the effective address of the operand is the instruction's address itself. Any…
Yukti Kumari
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What is offset in ARM Assembly? How does it work?

I am learning ARM Assembly Language. I do is write a program in c and compile it to look at the Assembly file. Below is such a compiled snippet from a program and it has this ldr r0, [pc, #28]. Here I need help in understanding this PC thing. I know…
pro_nav
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