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Questions tagged [addressing-mode]

An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

From Wikipedia (Addressing mode):

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

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Invalid effective address - subtracting two registers

mov edi, 4 mov ecx, 10 read: lea eax, [ebp-edi] ;error line push eax call readVal add edi, 4 loop read add esp, 40 I am trying to allocate an array of 10 elements of a…
Rheagar
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How to read memory with segment addressing mode in lldb on x86-64?

While debugging a process with lldb I get to this assembly instruction: -> 0x7ffff79c5187 <+7>: movq %fs:(%r14), %r14 Or in intel syntax: -> 0x7ffff79c5187 <+7>: mov r14, qword ptr fs:[r14] Contents of the registers: (lldb) register…
talz
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Word Addressing in a Single Processor Cache

I've recently come across this description of a single processor cache saying that it's "Word addressed (addresses are left shifted by 2 by adding “00” to end of address inside the processor, this implies that it can address 2^32*4 = 16GBytes of…
johnoldman
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How would I use base addressing mode to save character into variable?

I'm new to Assembly and learning the basics, but i've been stuck for a while on this and don't know how to get past it. The code below works, but not using the required base addressing mode. I have to copy the fifth character from String into the…
mexicanburrito
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Invalid effective address when using big factor

I'm trying to read from a reserved memory in NASM using the following instructions: movzx eax, [mat+100*edi+esi] mov [dmat+298*edi+3*esi], eax But I get the following error invalid effective address invalid effective address: two index…
user19980548
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In a RISC/MIPS-32bit architecture, how does an instruction target a remote memory address that falls out of the offset?

From what I understand, RISC architecture like MIPS, uses a fixed-length instruction. For branching and jumping between memory, and respectively J or I type - we are given a section inside to allocate 16 or 26 bits to offsets from the current memory…
cozycoder
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error: invalid operand type when mutiplying by register

I am making a program in x86_64 assembly language and it requires me to offset a memory address by a variable. I am trying to use the * to multiply the address by edx however, I get the following error: kernel.asm:23: error: invalid operand…
Markian
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`i2cdetect` command shows multiple slave addresses for single device

I am working on a project where I need to communicate my slave device EEPROM (Slave address as 0x54). But when I gave the i2cdetect -r -y 10 command it shows 8 different addresses for single hardware. I had configured the hardware by device…
chandru
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How to do relative addressing in GAS syntax

So I'm trying to write a function to zero out an input buffer in static memory in my assembly program. It looks like this: zero_input_buffer: mov $0, %ebx mov $29, %eax # not sure how to implement this line mov %ebx, input(%rip,…
Dyskord
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Finding values of registers via AT&T syntax operands

I'm a little confused about how to derive/calculate the values of registers. I've scoured several questions on SO and other websites but I can't find anyone who has addressed my question. Here's where my confusion lies. Suppose we have the following…
Maximus T.
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What is the difference between putting a 32-bit and a 64-bit register in the effective address?

When I assemble this (with nasm), extern L jmp [eax + ebx * 2 + L] jmp [rax + rbx * 2 + L] jmp [eax + L] jmp [rax + L] the result is, 67 ff a4 58 ... ff a4 58 ... 67 ff a0 ... ff a0 ... There is an additional 0x67 in the resulting binary for…
xiver77
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Syntax for indirect jump in GAS (Intel syntax): double brackets and/or OFFSET as part of the addressing mode?

For an indirect jump to the address stored in L + 8 in 64-bit mode, nasm accepts, jmp [L + 8] jmp qword [L + 8] GNU as accepts, jmp [L + 8] jmp qword ptr [L + 8] and also, jmp [[L + 8]] jmp [qword ptr [L + 8]] even more, jmp qword ptr [offset L +…
xiver77
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Type of addressing mode for [bx]?

I've been stuck trying to figure out the addressing mode of this instruction. Mov dl, byte ptr[bx]
Mouhib Boucherika
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Assembler HCS12 how does register with index work with TST-instruction?

Hello this is my test code: LDX #$2000 LDY #$1000 LDD #$0000 la: ADDD #1 MOVB 1, X+, 1, Y+ TST -1, X <-- what do I check here? BNE la My question is what do I…
kanat0x61
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Does offset in ARM Assembly counts from the start or the end?

i am very new to ARM assembly and i want to understand how the actual machine code looks like when you're storing using STUR. To give you an example here's 64 bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Now…
Areg
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