0

I'm trying to access eMMC soldered to Intel SDIO controller on Intel Atom z8350 platform. The documentation says that there are 3 controllers in the SoC, but PCI scanning finds only one one that is not connected to the card. Research shows that the one controller with eMMC is hidden from PCI space. It is available through the ACPI and ACPI tables has information about it (including BARs). Also I found out that GRUB (via lspci) can touch it. But when Linux has been booted lspci don't see it and eMMC is attached via sdhci-acpi.c in kernel.

Reading documentation showed that the device can operates in ACPI-mode and PCI-mode. But I don't found any information how to switch that modes.

I want to return that controller to PCI space. Can someone provide me with additional information?

acckiitvar
  • 25
  • 5
  • Why do you want that? What do you want to achieve? For the end user (let's say General Purpose OS, like Linux) the ACPI is good enough and provides all necessary resources. – 0andriy Aug 18 '23 at 19:34
  • I have my own OS and support ACPI is too big step at this point (ACPICA is in future tasks). But HW have that strange behaviour that ruins my plans. – acckiitvar Aug 21 '23 at 17:51
  • I see. You need to update BIOS to support that. Perhaps Coreboot has that capability. Note, it’s **not** as easy as Boolean switch, the hardware should be programmed correctly to be able to appear as PCI compatible device. And actually I’m not sure about SDHCI, there are too many nuances behind the scenes. – 0andriy Aug 21 '23 at 23:40
  • The easiest way is to enable ACPICA in your OS. The hackish approach (as proof-of-concept) is to hardcore data for now in your code. – 0andriy Aug 21 '23 at 23:42
  • Here is the coreboot source tree: https://github.com/coreboot/coreboot/tree/master/src/soc/intel/braswell. – 0andriy Aug 22 '23 at 00:11
  • 1
    Here we are: https://review.coreboot.org/plugins/gitiles/coreboot/+/d94cff6ab26d482554309041a9317cc3bf5e4b02/src/soc/intel/braswell/southcluster.c#203. It seems that by default devices are available via PCI programming interface. That makes your task easier to accomplish. – 0andriy Aug 22 '23 at 02:09
  • 1
    Thank you very much. I think https://review.coreboot.org/plugins/gitiles/coreboot/+/d94cff6ab26d482554309041a9317cc3bf5e4b02/src/soc/intel/baytrail/smihandler.c#253 is what I need. It is a big question could I reproduce it, but it is a way. – acckiitvar Aug 24 '23 at 08:28
  • Yes, some communication via IOSF SideBand. But see the difference, what I pointed out is for Braswell (the SoC that you referred in your question), and what you found is for Bay Trail (which is previous generation). In the former the PMC firmware seems to take care about IOSF SB programming, while in the latter it needs to be done in software. – 0andriy Aug 25 '23 at 03:21
  • OTOH, _iosf.h_ for Braswell is quite similar to the Bay Trail one, it might be that PMC only disables / enables the device on the bus (like cutting power from it completely, D3cold analogue) and IOSF SB is needed to have it switched between ACPI and PCI programming interface. In any case you got the idea. – 0andriy Aug 25 '23 at 03:34

0 Answers0