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I was reading about how PCI bus gets to find the information about a PCI device before any transaction can take place. Please check the excerpt below.

For example, in case of a PCI memory device, how does the PCI bus/controller get to know about the size of the memory device like if it is one-Megabyte and the address range used by it? I think one MB memory needs 2^20 addresses. Is this information stored in some sort of register(s)?

Likewise, how does a PCI bus or controller gets to know about the wait states used by a memory device for read and write operation? For example, the PCI memory might need 3 wait cycles for the read operation. Is this information stored in some sort of register(s)?

How does PCI determines the size of memory

Source: PCI Bus Demystified by Abbott, 2nd ed, Pg. 89

I went to through a chapter of the mentioned book but couldn't really get the answer. I'm trying to understand it at a basic level and I'm a beginner.

PG1995
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    The BAR encodes the start **and** the size of an IO/memory region. The memory transaction **has** to get to the PCI bus segment where the device resides. If there is only one bus that's easy: all transactions are made on this bus. If there are other busses, then a PCI-to-PCI bridge is required and this bridge has a configurable window and all addresses within it are relayed on the secondary bus (and vice versa). As for the wait states that are taken care of by the PCI protocol. There's a signal to assert when data is ready. – Margaret Bloom Nov 18 '22 at 13:13
  • @MargaretBloom Thank you for the help! I think this BAR is a physical register(s) located on a PCI device. Could you please confirm? The excerpt says the following. *“**BAR that represents 1 Megabyte of memory space would only need to implement the upper 12 bits of the 32 bit address. The lower 20 bits decode an address within the 1 Megabyte range.**”* Why would it implement upper 12 bits? 1 Megabyte only requires 20 lower bits. – PG1995 Nov 19 '22 at 08:31
  • Please check this: i.stack.imgur.com/63d9b.png , pg. 19 of the same book. The PCI master could find information about the initial target latency from... information encoded in some register but where does the information resides about the wait states used by a PCI memory device for its read and write operations. Suppose it needs 3 wait cycles for the read operation and 1 wait cycle for the write cycle. – PG1995 Nov 19 '22 at 08:34
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    BARs are implemented by the PCI device yes. A 1MiB memory region needs 20 bits to be addressed. If 20 bits are used to address a byte in the 1MiB region, of the 32 bits possible of the full address space, 12 are left for decoding the region position in the full address space. I don't understand your last question. As the book highlight, there are signals asserted to mark the time the device becomes ready. The master just waits, giving up after a standardized amount of time (eg: 16 and 8 cycles as pointed in the book). – Margaret Bloom Nov 19 '22 at 09:30
  • @MargaretBloom I really appreciate your help. I think you’re saying that the total address space for the PCI device could use 32 bits but actual 20-bit memory region for 4 MB device could lie anywhere between the full address space. For example, among many other possibilities, the addresses could extend from 00000000_0000_00000000_00000000_0000 to 00000000_0000_11111111_11111111_1111, or it could extend from 11111111_1111_00000000_00000000_0000 to 11111111_1111_11111111_11111111_1111. BTW, does BAR also encode address the DEVSEL so that the PCI device could be located by the PCI controller? – PG1995 Nov 19 '22 at 13:06
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    The size of a MMIO region also implies its alignment. A 4MiB size region must be aligned on 4MiB (so it must be at addresses like 0MiB, 4MiB, 8MiB, 12MiB, ...). If you look at addresses like those, you see that the low log2(4MiB) = 22 bits are always zero. So the device only needs to check the remaining ones. The alignment is a nice requirement. It's also useful because the specs (and the book) says that if you write all 1s in a BAR and read it back, the bits not used for decoding are turned into zero. So by counting them you can tell the size of the MMIO of any device without the need for ... – Margaret Bloom Nov 19 '22 at 13:25
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    ... a datasheet. DEVSEL is asserted by the device when it detects to be the target of a transaction.[Wikipedia has a section on how it's used](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect#Address_phase). – Margaret Bloom Nov 19 '22 at 13:26
  • @MargaretBloom Thanks a lot for your help! For 32 bit PCI during the address phase AD[1:0] are not used. Therefore, isn't there a subtle mistake when it says, **"*BAR that represents 1 Megabyte of memory space would only need to implement the upper 12 bits of the 32 bit address. The lower 20 bits decode an address within the 1 Megabyte range*"""? Wouldn't it need lower 20 bits (i.e. from AD[21:2]) for 1 Megabyte of memory space which only leaves 10 bits remaining (i.e. from AD[31:22]). Where am I going wrong? Also, are AD lines asserted LOW or HIGH? Could you please help me? – PG1995 Nov 20 '22 at 10:25
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    Yes, my mistake. `AD[1:0]` are not used, so only 20-2 = 18 bits are used to address into the 1MiB region. Signals whose name ends in a `#` are asserted low (eg: `DEVSEL#`), all the other ones are asserted high (including `AD`s). – Margaret Bloom Nov 20 '22 at 18:05

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