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I'm looking into the capabilities of fragment/packet reassembly hardware and wondering whether one could use them to perform application-level packet reassembly.

I have to receive and reassemble a sequence of 65kiB packets (hundreds of streams adding up to 200 or 400Gbit/s) that I need to reorder and assemble (amounting e.g. to large 512kiB frames) in my application before delivering them further to other computation.

Would any existing receive offload hardware be able to help here? Instead of 'just' reassembling on ip+tcp would I be able to tell it to reassemble on ip+udp+ my application level fragment/segment protocol?

Apart from using a custom FPGA, I mean.

edit: I'm working on a Mellanox Connect-x 6 dx NIC, dpdk 21.11, fw 22.32.1010

Touisteur EmporteUneVache
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  • Can you please rephrase your question about `dpdk`, the current library in DPDK helps to fragment and reassemble packets. But you are mentioning about `fragment/packet reassembly hardware`. So is your question `are there any RX or TX offloads which denotes reassembly and fragment in DPDK?` or are you asking `for my use case 65KiB fragment flows will hardware help`? – Vipin Varghese May 26 '22 at 03:30
  • Sorry if I'm imprecise. I was wondering whether there were RX offload hardware that could (be programmed to) reassemble/reorder/batch several (already reassembled themselves ip+udp) packets together following a user-provided reassembly protocol, and if it was accessible through dpdk. 65KiB is the size of one reassembled ip+udp packet, and I have many of those to then stitch together to form a larger packet. – Touisteur EmporteUneVache May 29 '22 at 22:06
  • Please update with DPDK version, NIC, firmware of the NIC to better help you – Vipin Varghese May 30 '22 at 04:32
  • thanks for the update `Mellanox Connect-x 6 dx NIC, dpdk 21.11, fw 22.32.1010`. The CX-6 NIC is 100Gbps or 200Gbps controller? – Vipin Varghese Jun 22 '22 at 03:24
  • the answer to your query is updated.if it has helped you accept and upvote to close the query. – Vipin Varghese Jun 28 '22 at 08:53

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There are multiple NICs under Mellanox connectx-6, but most of them are classified as SMART NIC. Some of them are referenced under 100Gbps and 200Gbp single and multiple-port PCIe Gen 4 as 1, 2, 3 and 4.

But all the NICs support certain fixed functionality, but not HW IP packet reassembly with connectx-6. With DPDK 22.03 there are options for RTE_ETH_DEV_REASSEMBLY_F_IPV4 |RTE_ETH_DEV_REASSEMBLY_F_IPV46 which is supported on Marvell OCTEON CN9K/CN10K SoC.

An alternative way is to make use of custom FPGA, DPU-2 Bluefield from Mellanox, Intel NetSec one can new create logic like ipv4|ipv6 reassembly.

Vipin Varghese
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