Is there an upper limit to parameter value in Verilog?

Question

I have a parameter defined as: parameter TARGET = 18000000000. The hexadecimal equivalent of this number is "4 30E2 3400". But when I am porting this design on FPGA and checking the waveform, I can see that 820130816 is getting passed. The hexadecimal equivalent of this number is "30E2 3400".

So, it seems that only lower 32-bits are getting considered here while the upper bits are getting ignored.

Can someone tell me is there any upper limit on parameter value that we can pass (in this case, 32-bits)? Or am I doing it incorrectly?

Does this answer your question? [Verilog: Non-integer parameters](https://stackoverflow.com/questions/18362402/verilog-non-integer-parameters) — Qiu, Jul 10 '20 at 07:08

score 0 · Accepted Answer · answered Jul 08 '20 at 13:22

parameter without specifying a type will use the type of the rhs expression. In you case the rhs expression is a 32-bit integer. Even though you specified a number which exceeds 32 bits, it gets truncated to the default width of 32. This is the width of the numeric constants without specification of their width.

So, in order to make it right you need to specify the width of the rhs literal. The following will do:

parameter TARGET = 64'd18000000000;

Is there an upper limit to parameter value in Verilog?

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