Verliog- comparator

Question

For two 3-bit unsigned numbers a (a2a1a0)and b (b2b1b0), build a logic circuit to output the larger number.
I want to compare three bits number and show the larger number. But the code can not work.
I cannot find the mistake i have made.

4.ABTB=A is bigger than B

module comparator(
    input [2:0]A,
    input [2:0]B,
    output reg [2:0]out,
    output ABTB,
    output ASTB,
    output AEQB
    );
assign ABTB=(A[2]&(~B[2]))||((~((A[2]&(~B[2]))||((~A[2])&B[2])))&(A[1]&(~B[1])))||((~((A[2]&(~B[2]))||((~A[2])&B[2])))&(~((A[1]&(~B[1]))||((~A[1])&B[1])))&(A[0]&(~B[0])));
assign ASTB=((~A[2])&B[2])||((~((A[2]&(~B[2]))||((~A[2]&B[2])))&((~A[1])&B[1])))||((~((A[2]&(~B[2]))||((~A[2])&B[2])))&(~((A[1]&(~B[1]))||((~A[1])&B[1])))&((~A[0])&B[0]));
assign AEQB=(~((A[2]&(~B[2]))||((~A[2])&B[2])))&(~((A[1]&(~B[1]))||((~A[1])&B[1])))&(~((A[0]&(~B[0]))||((~A[0])&B[0])));

always@*
if(ABTB==1)
assign out=A;
else if(ASTB==1)
assign out=B;
else if(AEQB==1)
assign out=A;


endmodule

module test_comparator;
    reg [2:0]A;
    reg [2:0]B;

    wire ABTB;
    wire ASTB;
    wire AEQB;
comparator u0(.a(a),.b(b),.abtb(abtb),.astb(astb),.aeqb(aeqb));

initial
begin

A=000;B=001;
#10 A=001;B=001;
#10 A=010;B=001;
#10 A=011;B=001;
#10 A=100;B=001;
#10 A=101;B=001;
#10 A=110;B=001;
#10 A=111;B=001;
#10 A=001;B=001;
#10 A=001;B=001;
#10 A=001;B=001;

end
endmodule

A/ Sorry but I am not going to check these insane complex expressions. Also I first would need to make a 64-entry truth table for that. Why not use a series of `if` statement or was the school assignment to have to do it in logic expressions? By the way: you need only two expressions. Maybe you can figure out what is wrong when your expressions contradict. B/ Do not use `assign` in an always @ section. — Oldfart, Mar 07 '20 at 09:40
64 entry truth table is beyond my capability. a series of if statement? Can you show me examples? Why I use complex expressions? because I did not have any ideas. — Henry, Mar 07 '20 at 10:20
I have found a simple way.but it still can not work.module compare( input [2:0]A, input [2:0]B, output [2:0]out ); assign out=(A>B)?A:B; endmodule — Henry, Mar 07 '20 at 10:45
The last one is the way to go in HDL. I suggest you update your question with the new code and explain why is still does not work: what you have and what you expect. By the way testing is easier with for loops. — Oldfart, Mar 07 '20 at 10:54

acmert · Accepted Answer · 2020-03-07T20:21:31.307

0

The condition (A>B) can be expressed as (for 3-bit inputs A and B):

assign Bit_3 = A[2] & (~B[2]);
assign Bit_2 = (A[2] ^~ B[2]) & (A[1] & (~B[1]));
assign Bit_1 = (A[2] ^~ B[2]) & (A[1] ^~ B[1]) & (A[0] & (~B[0]));

assign ABTB = (Bit_3 | Bit_2 | Bit_1);

Then you can set out as:

assign out = (ABTB) ? A : B;

edited Mar 07 '20 at 20:21

answered Mar 07 '20 at 11:16

acmert

129
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Did you test that code or just wrote it down? I found your expressions weird and tested them. They rather failed. e.g. if A=1 it only reports A>B if B = 6.... – Oldfart Mar 07 '20 at 17:44
Should have tested it, my bad. XOR gates (`^`) in the code should be XNOR (`^~`). Fixed it, thanks! – acmert Mar 07 '20 at 20:23

Verliog- comparator

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