Illegal redeclaration of 'synaptic_core'

Question

I am compiling an SNN simulator named "ODIN" in Xilinx. for the name of the module i get this error. Can you help me with this?

Illegal redeclaration of 'synaptic_core'

module synaptic_core #(
parameter N = 256,
parameter M = 8
)(

// Global inputs ------------------------------------------
input  wire           RSTN_syncn,
input  wire           CLK,

// Inputs from SPI configuration registers ----------------
input  wire           SPI_GATE_ACTIVITY_sync,
input  wire [  N-1:0] SPI_SYN_SIGN, 
input  wire           SPI_UPDATE_UNMAPPED_SYN,

// Inputs from controller ---------------------------------
input  wire [    7:0] CTRL_PRE_EN,
input  wire           CTRL_BIST_REF,
input  wire           CTRL_SYNARRAY_WE,
input  wire [   12:0] CTRL_SYNARRAY_ADDR,
input  wire           CTRL_SYNARRAY_CS,
input  wire [2*M-1:0] CTRL_PROG_DATA,
input  wire [2*M-1:0] CTRL_SPI_ADDR,

// Inputs from neurons ------------------------------------
input  wire [  N-1:0] NEUR_V_UP,
input  wire [  N-1:0] NEUR_V_DOWN,

// Outputs ------------------------------------------------
output wire [   31:0] SYNARRAY_RDATA,
output wire [   31:0] SYNARRAY_WDATA,
output wire           SYN_SIGN

);

Answer 1

You probably declared the 'synaptic_core' somewhere before in the code.

From the https://www.xilinx.com/support/answers/18361.html :

Examine your Verilog code prior to the line number listed in the error to see where the name listed has been declared. The name might have been used in a different manner (as a module name, parameter, task, function, etc.) or referenced in a different file (accessed by an "include statement," for example).

Answer 2

Most likely you tried to compile this module twice on the same command line.