setting the output reg of one device to be the input of another device in verilog

Question

i want the value of the output reg of a module to be used as input of another module .How can I do so ? the following code shows errors when i try to connect the output of a 3 bit upcounter to a 3to8 decoder

module combouno(clk,enb,rest,dec);
input clk,enb,rest;
output reg [7:0]dec;
 wire [2:0]Q;
thrbitup uno(clk,Q,enb,rest);   
egtbtdec dec1(Q,dec);
endmodule
module thrbitup(clkk,q,en,res);
input clkk,en,res;
output reg [2:0]q;
always@(posedge clkk,negedge res)

if(res==0)
q<=0;

else if(en)
q<=q+1;


endmodule

module egtbtdec(x,y);
input [2:0]x;
output reg [7:0]y;

always@(x)
begin
case(x)
3'b000 : y=8'b00000001;
3'b001 : y=8'b00000010;
3'b010 : y=8'b00000100;
3'b011 : y=8'b00001000;
3'b100 : y=8'b00010000;
3'b101 : y=8'b00100000;
3'b110 : y=8'b01000000;
3'b111 : y=8'b10000000;
endcase
end 
endmodule

the error is as follows Error (10663): Verilog HDL Port Connection error at combouno.v(6): output or inout port "y" must be connected to a structural net expression

score 0 · Answer 1 · answered Oct 04 '19 at 13:24

Your port should only be 'reg' in the place where you assign the values.

Any other ports in the hierarchy which pass this signal do not need to know if the original port was a reg or wire.

Thus remove the reg in the top level module:

module combouno(clk,enb,rest,dec);
input clk,enb,rest;
output [7:0]dec;

Anyway it is better to switch to the ANSI port style:

module combouno
   (
   input clk,enb,rest, 
   output [7:0]dec  
   );

Also check for typing errors: you are using 'res' and 'rest'.

setting the output reg of one device to be the input of another device in verilog

1 Answers1